EP2S15 datasheet(28/238 Pages) ALTERA

28 / 238 page

2–20

Altera Corporation

Stratix II Device Handbook, Volume 1

May 2007

Adaptive Logic Modules

arithmetic chain runs vertically allowing fast horizontal connections to

TriMatrix memory and DSP blocks. A shared arithmetic chain can

continue as far as a full column.

Similar to the carry chains, the shared arithmetic chains are also top- or

bottom-half bypassable. This capability allows the shared arithmetic

chain to cascade through half of the ALMs in a LAB while leaving the

other half available for narrower fan-in functionality. Every other LAB

column is top-half bypassable, while the other LAB columns are bottom-

half bypassable.

See the “MultiTrack Interconnect” on page 2–22 section for more

information on shared arithmetic chain interconnect.

In addition to the general routing outputs, the ALMs in an LAB have

same LAB to be cascaded together. The register chain interconnect allows

an LAB to use LUTs for a single combinational function and the registers

to be used for an unrelated shift register implementation. These resources

speed up connections between ALMs while saving local interconnect

resources (see Figure 2–15). The Quartus II Compiler automatically takes

advantage of these resources to improve utilization and performance.

EP2S15 Datasheet(PDF) 28 Page - Altera Corporation