TCM4400EPET datasheet(41/64 Pages) TI

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TCM4400E

GSM/DCS BASEBAND AND VOICE A/D

AND D/A RF INTERFACE CIRCUIT

SLWS082A – JULY 1999 – REVISED MARCH 2000

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

MCU serial baseband digital interface

The GSM baseband and voice A/D and D/A conversion provide two digital serial 16-bit interfaces intended for

use with the DSP and a microcontroller device. Through this interface a microcontroller can access all the

internal registers that can be accessed through the DSP digital serial interface.

This option is intended for an application in which a part of layer-1 software is implemented into the

microcontroller needs access to some functions implemented into the GSM baseband and voice A/D and D/A

conversion circuitry.

serial interface

The microcontroller serial interface is designed to be compliant with 8-bit standard synchronous serial ports.

This interface consists of four terminals (see Figure 3 for timing diagram).

UCLK:

A clock provided by the microcontroller to GSM baseband and voice A/D and D/A conversion

UDR:

An input terminal of the GSM baseband and voice A/D and D/A components intended for reception

of data

UDX:

An output terminal of the GSM baseband and voice A/D and D/A components intended for

transmission of data

USEL:

An input terminal of GSM baseband and voice A/D and D/A components intended for activation

of the serial interface

When USEL = VDD, the serial interface is deactivated and UDX is placed in a high-impedance state. A high level

on USEL resets the internal serial interface; the 16-bit transfers must be completed with USEL = VSS.

The external MCU initiates data transfer by driving the selection terminal and sending a clock signal. For both

the GSM baseband and voice A/D and D/A components, the MCU data is shifted out of the shift registers on

one edge of the clock and latched into the shift registers on the opposite clock edge.

As a result, both controllers send and receive data simultaneously. For the MCU portion, the software

determines whether the data is meaningful or dummy data. On the GSM baseband and voice A/D and D/A

conversion portion, dummy data is data with all zeroes.

The 16-bit word data format is identical to the DSP data format. After a read-register command, there is a

sequential transfer delay between two 16-bit word acquisitions to let the internal sequencer extract the data

going from internal registers to the serial shift register.

Three internal bits control the data serial flow as follows:

• UDIR determines whether data is transferred with MSB or LSB first.

• UPOL determines the polarity of the clock.

• UPHA determines the insertion of a half-clock period in the data serial flow.

With UPOL and UPHA there are four clock schemes (see Table 2):

• Falling edge without delay. The MCU serial interface transmits data on the falling edge of the UCLK and

receives data on the rising edge of the UCLK.

• Fallingedgewithdelay.TheMCUserialinterfacetransmitsdataonehalf-cycleaheadofthefallingedge

of the UCLK and receives data on the falling edge of the UCLK.

• Rising edge without delay. The MCU serial interface transmits data on the rising edge of the UCLK and

receives data on the falling edge of the UCLK.

• Rising edge with delay. The MCU serial interface transmits data one half-cycle ahead of the rising edge

of the UCLK and receives data on the rising edge of the UCLK.

TCM4400EPET Datasheet(PDF) 41 Page - Texas Instruments

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