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TCM4400EPET Datasheet(PDF) 49 Page - Texas Instruments |
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TCM4400EPET Datasheet(HTML) 49 Page - Texas Instruments |
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49 / 64 page ![]() TCM4400E GSM/DCS BASEBAND AND VOICE A/D AND D/A RF INTERFACE CIRCUIT SLWS082A – JULY 1999 – REVISED MARCH 2000 49 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PRINCIPLES OF OPERATION power down register No. 1 The values in each bit position of power down register No. 1 have the meaning outlined in Table 14. Table 14. PWDNRG1 Register PWDNRG1: REGISTER FOR POWERING DOWN ADDRESS: 7 R/W SELVMID BALOOP VMIDW VMIDPD BBULW BBULPD BBDLW BBDLPD EXTCAL BBRST 0 0 1 1 1 1/0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W <–ACCESS TYPE 0 0 0 0 0 0 0 0 0 0 <–VALUE AT RESET BBRST: This is the digital reset of the baseband codec (active at 1); the uplink burst buffer is loaded with all 1s and the memory and registers of the downlink digital filter is cleared to 0. This is not a toggle bit as it has to be set to 0 to remove the reset condition. EXTCAL: Downlink autocalibration mode (at 0: autocalibration; at 1: external calibration) BBULW: If cleared to 0, the baseband uplink path is powered down under the control of the GSM transmit window (BULON terminal). If this bit is set to 1, the power down is only controlled by bit BBULPD. BBULPD: This bit is functionally associated with bit BBULW. When this bit is set to 1, the baseband uplink path is in power-down mode. BBDLW: If cleared to 0, the baseband downlink path is powered down under the control of GSM receive window (BDLON terminal). If this bit is set to 1, the power down is only controlled by bit BBDLPD. BBDLPD: This bit is functionally associated with bit BBDLW. When this bit is set to 1, the baseband downlink path is in power-down mode. VMIDW: If cleared to 0, the VMID output driver is powered down under the control of GSM transmit window (BULON terminal). If this bit is set to 1, the power down is only controlled by bit VMIDPD. VMIDPD: This bit is functionally associated and paired with bit VMIDW. When VMIDW bit is set to 1, the VMID output driver is active. When VMIDPD bit is set to 1, the VMID output driver is in power-down mode. BALOOP: When set to 1, the internal analog loop of I and Q uplink terminals are connected to I and Q downlink terminals. SELVMID: When cleared to 0, this sets the common-mode voltage of the baseband uplink and VMID at VDD/2; when set to 1, these voltages are set to 1.35 V. |
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