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TCM4400EPET Datasheet(PDF) 47 Page - Texas Instruments

Part # TCM4400EPET
Description  GSM/DCS BASEBAND AND VOICE A/D AND D/A RF INTERFACE CIRCUIT
PDF  64 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TCM4400EPET Datasheet(HTML) 47 Page - Texas Instruments

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TCM4400E
GSM/DCS BASEBAND AND VOICE A/D
AND D/A RF INTERFACE CIRCUIT
SLWS082A – JULY 1999 – REVISED MARCH 2000
47
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
baseband uplink I and Q offset registers
The baseband uplink I and Q offset registers contain the offset values for the I and Q components, respectively,
as shown in Tables 9 and 10.
Table 9. Uplink I Offset Register
BULIOFF: BASEBAND UPLINK I OFFSET REGISTER
ADDRESS: 3
R/W
RESERVD
ULIOFF8
ULIOFF7
ULIOFF6
ULIOFF5
ULIOFF4
ULIOFF3
ULIOFF2
ULIOFF1
ULIOFF
0 0 0 1 1
1/0
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
<–ACCESS TYPE
0
0
1
1
1
1
1
1
1
1
<–VALUE AT RESET
ULIOFF0 to ULIOFF1
: Integration bits during calibration (to minimize sensitivity to noise)
ULIOFF2 to ULIOFF8
: Value of the offset on I channel
RESERVD
: Reserved bits for testing purposes
R/W
: A 1 indicates a read operation; a 0 indicates a write operation.
Table 10. Uplink Q Offset Register
BULQOFF: BASEBAND UPLINK Q OFFSET REGISTER
ADDRESS: 4
R/W
RESERVD
ULQOFF8
ULQOFF7
ULQOFF6
ULQOFF5
ULQOFF4
ULQOFF3
ULQOFF2
ULQOFF1
ULQOFF0
0
0
1
0
0
1/0
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
<–ACCESS TYPE
0
0
1
1
1
1
1
1
1
1
<–VALUE AT RESET
ULQOFF0 to ULQOFF1 : Integration bits during calibration (to minimize sensitivity to noise)
ULQOFF2 to ULQOFF8 : Value of the offset on Q channel
RESERVD
: Reserved bits for testing purposes
R/W
: A 1 indicates a read operation; a 0 indicates a write operation.
baseband uplink I and Q D/A conversion registers
The I and Q component values generated by the I and Q uplink D/A converter during the conversion of analog
data are written to and read from the uplink I and Q D/A converter registers as shown in Tables 11 and 12.
Table 11. Uplink I DAC Register
BULIDAC: BASEBAND UPLINK I DAC REGISTER
ADDRESS: 6
R/W
RESERVD
RESERVD
RESERVD
RESERVD
RESERVD
RESERVD
RESERVD
RESERVD
RESERVD
RESERVD
0
0
1
1
0
1/0
R
R
R
R
R
R
R
R
R
R
<–ACCE0S TYPE
0
0
0
0
0
0
0
0
0
0
<–VALUE AT RESET
RESERVD
: Reserved bits for testing purposes



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