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TCM4400EPET Datasheet(PDF) 8 Page - Texas Instruments

Part # TCM4400EPET
Description  GSM/DCS BASEBAND AND VOICE A/D AND D/A RF INTERFACE CIRCUIT
PDF  64 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TCM4400EPET Datasheet(HTML) 8 Page - Texas Instruments

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TCM4400E
GSM/DCS BASEBAND AND VOICE A/D
AND D/A RF INTERFACE CIRCUIT
SLWS082A – JULY 1999 – REVISED MARCH 2000
8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
voltage references
REFERENCE
MIN
TYP
MAX
UNIT
VGAP
Voltage on band gap (used for all other references)
1.16
1.22
1.28
Vdc
Band gap output resistance
200
K
Ω
Band gap external decoupling capacitance
0.1
µF
Band gap start time ( bit CHGUP=0 )
100
ms
Band gap start time ( bit CHGUP=1)
2.5
ms
VREF
Voltage reference of GMSK internal ADC and DAC : VVREF
1.66
1.75
1.84
Vdc
Voltage reference output resistance
200
K
Ω
Voltage reference external decoupling capacitance
0.1
µF
Voltage reference start time ( bit CHGUP=0 )
300
ms
Voltage reference start time ( bit CHGUP=1)
10
ms
VMID
Common-mode reference for baseband uplink: VVMID (Bit SELVMID=0)
–10%
Vdd/2
10%
Vdc
Common-mode reference for baseband uplink: VVMID (Bit SELVMID=1)
1.25
1.35
1.45
Vdc
Load resistance on Vmid output
10
K
Ω
MICBIAS
Microphone-driving voltage (Bit MICBIAS=0)
1.80
2.00
2.20
Vdc
Microphone-driving voltage(Bit MICBIAS=1)
2.25
2.5
2.75
Vdc
Microphone-bias current drive capability (Bit MICBIAS= 1)
450
500
µA
Microphone-bias current drive capability (Bit MICBIAS=0 )
350
400
µA
ADCMID
DC bias reference of the auxiliary ADCs
–10%
Vdd/2
10%
Vdc
ADCMID external decoupling capacitance
0.1
µF
IBIAS
Bias current adjust external resistance
100
K
Ω
master clock input (MCLK)
PARAMETER
MIN
NOM
MAX
UNIT
Master clock signal frequency
13
MHz
Master clock duty cycle (Sinewave)
40%
60%
Maximum peak-to-peak amplitude
1.3
Vpp
Minimum peak-to-peak amplitude
0.5
Vpp
Common-mode input voltage
VSS +0.5
VDD –0.5
Vdc
Input resistance at 13MHz (MCLK to ground)
4.1
5
6.5
K
Ω
Input capacitance at 13 MHz (MCLK to ground)
12.5
15
18
pf
baseband uplink path
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
I and Q D/A converters resolution
8
bit
Dynamic range on each output
Centered on VVMID
VVREF
Vpp
Differential output dynamic range with OUTLEV bit = 0†
BULQP-BULQN or BULIP-BULIN
2x VVREF
Vpp
Differential output dynamic range with OUTLEV bit = 1†
BULQP-BULQN or BULIP-BULIN
8/15 x VVREF
Vpp
Output load resistance, differential
10
k
Ω
Output load capacitance, differential
50
pF
Output common-mode voltage
Programmable by bit SELVMID
VVMID
V
I & Q output state in power down
Hi-Z
† Initial value after reset and at beginning of each burst are BULIP–BULIN=VREF and BULQP–BULQN=0 corresponding to a phase angle of 0°.



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