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TCM4400EPET Datasheet(PDF) 46 Page - Texas Instruments

Part # TCM4400EPET
Description  GSM/DCS BASEBAND AND VOICE A/D AND D/A RF INTERFACE CIRCUIT
PDF  64 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TCM4400EPET Datasheet(HTML) 46 Page - Texas Instruments

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TCM4400E
GSM/DCS BASEBAND AND VOICE A/D
AND D/A RF INTERFACE CIRCUIT
SLWS082A – JULY 1999 – REVISED MARCH 2000
46
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
baseband uplink data buffer
The baseband uplink data buffer is used to transmit the uplink burst data. The uplink data buffer contents are
shown in Table 8.
Table 8. Uplink Data Buffer
BULDATA: BASEBAND UPLINK DATA BUFFER
ADDRESS: 2 (16 WORDS)
W
BIT0
BIT1
BIT2
BIT3
BIT4
BIT5
BIT6
BIT7
BIT8
BIT9
0
0
0
1
0
0
BIT10
BIT11
BIT12
BIT13
BIT14
BIT15
BIT16
BIT17
BIT18
BIT19
0
0
0
1
0
0
BIT20
BIT21
BIT22
BIT23
BIT24
BIT25
BIT26
BIT27
BIT28
BIT29
0
0
0
1
0
0
BIT30
BIT31
BIT32
BIT33
BIT34
BIT35
BIT36
BIT37
BIT38
BIT39
0
0
0
1
0
0
BIT40
BIT41
BIT42
BIT43
BIT44
BIT45
BIT46
BIT47
BIT48
BIT49
0
0
0
1
0
0
BIT50
BIT51
BIT52
BIT53
BIT54
BIT55
BIT56
BIT57
BIT58
BIT59
0
0
0
1
0
0
BIT60
BIT61
BIT62
BIT63
BIT64
BIT65
BIT66
BIT67
BIT68
BIT69
0
0
0
1
0
0
BIT70
BIT71
BIT72
BIT73
BIT74
BIT75
BIT76
BIT77
BIT78
BIT79
0
0
0
1
0
0
BIT80
BIT81
BIT82
BIT83
BIT84
BIT85
BIT86
BIT87
BIT88
BIT89
0
0
0
1
0
0
BIT90
BIT91
BIT92
BIT93
BIT94
BIT95
BIT96
BIT97
BIT98
BIT99
0
0
0
1
0
0
BIT100
BIT101
BIT102
BIT103
BIT104
BIT105
BIT106
BIT107
BIT108
BIT109
0
0
0
1
0
0
BIT110
BIT111
BIT112
BIT113
BIT114
BIT115
BIT116
BIT117
BIT118
BIT119
0
0
0
1
0
0
BIT120
BIT121
BIT122
BIT123
BIT124
BIT125
BIT126
BIT127
BIT128
BIT129
0
0
0
1
0
0
BIT130
BIT131
BIT132
BIT133
BIT134
BIT135
BIT136
BIT137
BIT138
BIT139
0
0
0
1
0
0
BIT140
BIT141
BIT142
BIT143
BIT144
BIT145
BIT146
BIT147
BIT148
BIT149
0
0
0
1
0
0
BIT150
BIT151
BIT152
BIT153
BIT154
BIT155
BIT156
BIT157
BIT158
BIT159
0
0
0
1
0
0
W
W
W
W
W
W
W
W
W
W
<–––ACCESS TYPE
1
1
1
1
1
1
1
1
1
1
<–––VALUE AT RESET
Bit 0 – Bit 159 are the bits composing the sequence of the transmitted burst, bit 0 is transmitted first. For a normal
burst, the uplink data buffer is loaded as follows:
Bit 0 to 3
: 4 guard bits
Bit 4 to 6
: 3 tail bits
Bit 7 to 66
: 58 data bits
Bit 67 to 92
: 26 training sequence bits
Bit 93 to 92
: 58 training sequence bits
Bit 151 to 153
: 3 tail bits
Bit 154 to 159
: 8 guard bits
At reset and after each transmission, the burst buffer is reinitialized with guard bits (all bits = 1). An address
pointer is incremented after each word written into the buffer so that next write operation affects the next word
of the buffer. This address pointer is set to the base address (Word 0) by a RESET, after transmission of a burst
or by setting the IBUFPTR bit to 1( this bit has to be set back to zero to release the address pointer).



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