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TCM4400EPET Datasheet(PDF) 19 Page - Texas Instruments |
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TCM4400EPET Datasheet(HTML) 19 Page - Texas Instruments |
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19 / 64 page  TCM4400E GSM/DCS BASEBAND AND VOICE A/D AND D/A RF INTERFACE CIRCUIT SLWS082A – JULY 1999 – REVISED MARCH 2000 19 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MCU serial interface timing requirements (see Figure 3) PARAMETER MIN NOM MAX UNIT tsu10 Setup time, UCLK stable before USEL ↓ 20 ns tv1 Hold time, UDX valid after USEL ↓ 20 ns tv2 Hold time, UDX valid after UCLK ↑ 20 ns th9 Sequential transfer delay between 16-bit word acquisition tw pulse duration, USEL high 3000 ns th10 Hold time, UCLK ↑ after USEL↓ 20 ns th11 Hold time, UCLK unknown after USEL ↑ 20 ns tsu11 Setup time, data valid before UCLK ↓ 20 ns th12 Hold time, data valid after UCLK ↓ 20 ns tc Cycle time, ULCK 154 ns DSP serial interface timing requirements (see Figure 4) PARAMETER MIN NOM MAX UNIT BCLKX BCLKX signal frequency ( Burst mode or Continuous mode depending on bit BCLKMODE) 13 MHz BCLKX BCLKX duty cycle 40% 50% 60% tsu12 Setup time, BFSX high before BCLKX ↓ 20 ns th12 Hold time, BFSX high after BCLKX ↓ 20 ns tsu13 Setup time, BDX valid before BCLKX ↓ 20 ns th13 Hold time, BDX valid after BCLKX ↓ 20 ns BCLKR BCLKR signal frequency (Output BCLKDIR = 0) 4.33 MHz BCLKR BCLKR signal frequency (Input BCLKDIR = 1) 13 MHz BCLKR BCLKR duty cycle 40% 50% 60% tsu14 Setup time, BFSR high before BCLKR ↓ 20 ns th14 Hold time, BFSR high after BCLKR ↓ 20 ns tsu16 Setup time, BDR valid before BCLKR ↓ 20 ns th15 Setup time, BDR valid after BCLKR ↓ 20 ns voice timing requirements (see Figure 5) PARAMETER MIN NOM MAX UNIT VCLK VCLK signal frequency ( Burst mode or Continuous mode depending on bit VCLKMODE) 520 kHz VCLK VCLK duty cycle 40% 50% 60% tsu7 Setup time, VFS high before VCLK ↓ 100 ns th6 Hold time, VFS high after VCLK ↓ 100 ns tsu8 Setup time, VDX valid before VCLK ↓ 100 ns th8 Hold time, VDX valid after VCLK ↓ 100 ns tsu9 Setup time, VDR valid before VCLK ↓ 100 ns th7 Hold time, VDR valid after VCLK ↓ 100 ns |
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