XIO2001 datasheet(101/131 Pages) TI

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5.8

Advanced Error Capabilities and Control Register

5.9

Header Log Register

XIO2001 PCI Express™ to PCI Bus Translation Bridge

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SCPS212B – MAY 2009 – REVISED JULY 2009

The advanced error capabilities and control register allows the system to monitor and control the

advanced error reporting capabilities. See Table 5-7 for a complete description of the register contents.

PCI Express extended register

118h

offset:

Read-only, Read/Write

Default value:

0000 00A0h

BIT NUMBER

RESET STATE

BIT NUMBER

RESET STATE

Table 5-7. Advanced Error Capabilities and Control Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

31:9

RSVD

Reserved. Returns 000 0000 0000 0000 0000 0000b when read.

8(1)

ECRC_CHK_EN

Extended CRC check enable

0 = Extended CRC checking is disabled

1 = Extended CRC checking is enabled

ECRC_CHK_CAPABLE

Extended CRC check capable. This read-only bit returns a value of 1b indicating that the

bridge is capable of checking extended CRC information.

6(1)

ECRC_GEN_EN

Extended CRC generation enable

0 = Extended CRC generation is disabled

1 = Extended CRC generation is enabled

ECRC_GEN_CAPABLE

Extended CRC generation capable. This read-only bit returns a value of 1b indicating

that the bridge is capable of generating extended CRC information.

4:0(1)

FIRST_ERR

First error pointer. This 5-bit value reflects the bit position within the uncorrectable error

status register (offset 104h, see Section 5.3) corresponding to the class of the first error

condition that was detected.

(1)

These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.

The header log register stores the TLP header for the packet that lead to the most recently detected error

condition. Offset 11Ch contains the first DWORD. Offset 128h contains the last DWORD (in the case of a

4DW TLP header). Each DWORD is stored with the least significant byte representing the earliest

transmitted. This register shall only be reset by a PCI Express reset (PERST), a GRST, or the

internally-generated power-on reset.

PCI Express extended register offset:

11Ch, 120h, 124h, and 128h

Read-only

Default value:

0000 0000h

BIT NUMBER

RESET STATE

BIT NUMBER

RESET STATE

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PCI Express Extended Configuration Space

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