XIO2001 datasheet(118/131 Pages) TI

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6.15 Cache Timer Upper Limit Register

XIO2001 PCI Express™ to PCI Bus Translation Bridge

SCPS212B – MAY 2009 – REVISED JULY 2009

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Table 6-11. Cache Timer Lower Limit Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

15:12

RSVD

Reserved. Returns 0h when read.

CACHE_TIMER

Minimum number of clock cycles that must have passed without a read hit on the

11:0(1)

_LOWER_LIMIT

completion data buffer before the "cache miss limit" check can be triggered.

(1)

These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.

Discard cached data after this number of clock cycles have passed without a read hit on the completion

data buffer. See Table 6-12 for a complete description of the register contents.

Device control memory window

56h

Read/Clear

Default value:

01C0h

BIT NUMBER

RESET STATE

Table 6-12. Cache Timer Upper Limit Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

15:12

RSVD

Reserved. Returns 0h when read.

CACHE_TIMER

Discard cached data after this number of clock cycles have passed without a read hit on

11:0(1)

_UPPER_LIMIT

the completion data buffer.

(1)

These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.

Memory-Mapped TI Proprietary Register Space

118

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