Electronic Components Datasheet Search
  English  ▼

X  

XIO2001 Datasheet(PDF) 120 Page - Texas Instruments

Click here to check the latest version.
Part # XIO2001
Description  Express??to PCI Bus Translation Bridge
PDF  131 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

XIO2001 Datasheet(HTML) 120 Page - Texas Instruments

Back Button XIO2001 Datasheet HTML 116Page - Texas Instruments XIO2001 Datasheet HTML 117Page - Texas Instruments XIO2001 Datasheet HTML 118Page - Texas Instruments XIO2001 Datasheet HTML 119Page - Texas Instruments XIO2001 Datasheet HTML 120Page - Texas Instruments XIO2001 Datasheet HTML 121Page - Texas Instruments XIO2001 Datasheet HTML 122Page - Texas Instruments XIO2001 Datasheet HTML 123Page - Texas Instruments XIO2001 Datasheet HTML 124Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 120 / 131 page
background image
7.3
Nominal Power Consumption
7.4
PCI Express Differential Transmitter Output Ranges
XIO2001 PCI Express™ to PCI Bus Translation Bridge
SCPS212B – MAY 2009 – REVISED JULY 2009
www.ti.com
DEVICES
POWER STATE(1)
VOLTS
AMPERES
WATTS
1.5
0.147
0.221
No downstream PCI devices
D0 idle
3.3
0.062
0.205
Totals:
0.209
0.426
1.5
0.148
0.222
One downstream PCI device
D0 idle
3.3
0.077
0.254
Totals:
0.225
0.476
1.5
0.157
0.236
One downstream PCI device
D0 active
3.3
0.165
0.545
Totals:
0.322
0.780
1.65
0.168
0.277
One downstream (max voltage)
D0 active
3.6
0.188
0.677
Totals:
0.356
0.954
(1)
D0 idle power state: Downstream PCI device is in PCI state D0. Downstream device driver is loaded. Downstream device is not actively
transferring data.
D0 active power state: Downstream PCI device is in PCI state D0. Downstream device driver is loaded. Downstream device is acitvely
transferring data (worst case scenario).
PARAMETER
TERMINALS
MIN
NOM
MAX
UNIT
COMMENTS
UI(1)
Each UI is 400 ps
±300 ppm. UI does not account for SSC
TXP, TXN
399.88
400
400.12
ps
Unit interval
dictated variations.
VTX-DIFF-PP
TXP, TXN
0.8
1.2
V
VTX-DIFF-PP = 2*|VTXP – VTXN|
Differential peak-to-peak output voltage
VTX-DIFF-PP-LOW
Low-power differential peak-to-peak TX
TXP, TXN
0.4
1.2
V
VTX-DIFF-PP = 2*|VTXP – VTXN|
voltage swing
This is the ratio of the VTX-DIFF-PP of the second and
VTX-DE-RATIO-3.5dB
TXP, TXN
3
4
dB
following bits after a transition divided by the VTX-DIFF-PP of
TX de-emphasis level ratio
the first bit after a transition.
TTX-EYE
(2) (3) (4)
TXP, TXN
0.75
UI
Does not include SSC or RefCLK jitter. Includes Rj at 10
–12.
Minimum TX eye width
TTX-EYE-MEDIAN-to-MAX-JITTER
(2)
Measured differentially at zero crossing points after
Maximum time between the jitter median
TXP, TXN
0.125
UI
applying the 2.5 GT/s clock recovery function.
and maximum deviation from the median
TTX-RISE-FALL
(2)
TXP, TXN
0.125
UI
Measured differentially from 20% to 80% of swing.
TX output rise/fall time
BWTX-PLL
(5)
TXP, TXN
22
MHz
Second order PLL jitter transfer bounding function.
Maximum TX PLL bandwidth
BWTX-PLL-LO-3DB
(5) (6)
TXP, TXN
1.5
MHz
Second order PLL jitter transfer bounding function.
Minimum TX PLL bandwidth
RLTX-DIFF
Tx package plus Si differential return
TXP, TXN
10
dB
loss
RLTX-CM
Tx package plus Si common mode return
TXP, TXN
6
dB
Measured over 0.05–1.25 GHz range
loss
(1)
SCC permits a 0, –5000 ppm modulation of the clock frequency at a modulation rate not to exceed 33 kHz.
(2)
Measurements at 2.5 GT/s require a scope with at least 6.2 GHz bandwidth. 2.5 GT/s may be measured within 200 mils of Tx device's
pins, although deconvolution is recommended.
(3)
Transmitter jitter is measured by driving the transmitter under test with a low jitter "ideal" clock and connecting the DUT to a reference
board.
(4)
Transmitter raw jitter data must be convolved with a filtering function that represents the worst case CDR tracking BW. After the
convolution process has been applied, the center of the resulting eye must be determined and used as a reference point for obtaining
eye voltage and margins.
(5)
The Tx PLL Bandwidth must lie between the min and max ranges given in the above table. PLL peaking must lie below the value listed
above. Note: the PLL B/W extends from zero up to the value(s) specified in the above table.
(6)
A single combination of PLL BW and peaking is specified for 2.5 GT/s implemenations.
Electrical Characteristics
120
Submit Documentation Feedback



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com