XIO2001 datasheet(122/131 Pages) TI

122 / 131 page

7.6

PCI Express Differential Reference Clock Input Ranges

(1)

XIO2001 PCI Express™ to PCI Bus Translation Bridge

SCPS212B – MAY 2009 – REVISED JULY 2009

www.ti.com

PCI Express Differential Receiver Input Ranges (continued)

PARAMETER

TERMINALS

MIN

NOM

MAX

UNIT

COMMENTS

BWRX-PLL-HI

(4)

RXP, RXN

MHz

Second order PLL jitter transfer bounding function.

Maximum Rx PLL bandwidth

BWRX-PLL-LO-3DB

(4)

RXP, RXN

1.5

MHz

Second order PLL jitter transfer bounding function.

Minimum Rx PLL for 3 dB peaking

VRX-CM-AC-P

(2)

VRX-CM-AC-P = RMS(|VRXP + VRXN|/2 – VRX-CM-DC)

RXP, RXN

150

AC peak common mode input voltage

VRX-CM-DC = DC(avg) of |VRXP + VRXN|/2.

RLRX-DIFF

(5)

Measured over 50 MHz to 1.25 GHz with the P and N

RXP, RXN

Differential return loss

lines biased at +300 mV and –300 mV, respectively.

RLRX-CM

(5)

Measured over 50 MHz to 1.25 GHz with the P and N

RXP, RXN

Common mode return loss

lines biased at +300 mV and –300 mV, respectively.

ZRX-DIFF-DC

(6)

RXP, RXN

120

Ω

RX dc differential mode impedance

DC differential input impedance

ZRX-DC

(5) (6)

Required RXP as well as RXN dc impedance (50

RXP, RXN

Ω

DC input impedance

Ω±20% tolerance).

ZRX-HIGH-IMP-DC-POS

(7)

Rx DC CM impedance with the Rx terminations not

DC input CM input impedance for V > 0

RXP, RXN

Ω

powered, measured over the range 0 to 200 mV with

during reset or powerdown

respect to ground.

ZRX-HIGH-IMP-DC-NEG

(7)

Rx DC CM impedance with the Rx terminations not

DC input CM input impedance for V > 0

RXP, RXN

Ω

powered, measured over the range 0 to 200 mV with

during reset or powerdown

respect to ground.

VRX-IDLE-DET-DIFFp-p

VRX-IDLE-DET-DIFFp-p = 2*|VRXP – VRXN| measured at the

RXP, RXN

175

Electrical idle detect threshold

receiver package terminals

An unexpected electrical idle

TRX-IDLE-DET-DIFF-ENTER-TIME

(VRX-DIFFp-p < VRX-IDLE-DET-DIFFp-p) must be recognized

Unexpected electrical idle enter detect

RXP, RXN

no longer than

threshold integration time

TRX-IDLE-DET-DIFF-ENTER-TIME to signal an unexpected idle

condition.

(4)

A single PLL bandwidth and peaking value of 1.5 to 22 MHz and 3 dB are defined.

(5)

The receiver input impedance results in a differential return loss greater than or equal to 15 dB with the P line biased to 300 mV and the

N line biased to .300 mV and a common mode return loss greater than or equal to 6 dB (no bias required) over a frequency range of 50

MHz to 1.25 GHz. This input impedance requirement applies to all valid input levels. The reference impedance for return loss

measurements for is 50 . to ground for both the P and N line (i.e., as measured by a Vector Network Analyzer with 50-. probes). The

series capacitors CTX is optional for the return loss measurement.

(6)

Impedance during all link training status state machine (LTSSM) states. When transitioning from a PCI Express reset to the detect state

(the initial state of the LTSSM) there is a 5-ms transition time before receiver termination values must be met on the unconfigured lane

of a port.

(7)

ZRX-HIGH-IMP-DC-NEG and ZRX-HIGH-IMP-DC-POS are defined respectively for negative and postive voltages at the input of the receiver.

PARAMETER

TERMINALS

MIN

NOM

MAX

UNIT

COMMENTS

fIN-DIFF

REFCLK+

The input frequency is 100 MHz + 300 ppm and –2800

100

MHz

Differential input frequency

REFCLK–

ppm including SSC-dictated variations.

fIN-SE

REFCLK+

The input frequency is 125 MHz + 300 ppm and –300

Single-ended input

125

MHz

ppm.

frequency

VRX-DIFFp-p

REFCLK+

Differential input

REFCLK–

-0.30

1.150

VRX-DIFFp-p = 2*|VREFCLK+ – VREFCLK-|

peak-to-peak voltage

REFCLK+

Single-ended, reference clock mode high-level input

VIH-SE

0.7 VDDA_33

VDDA_33

voltage

REFCLK+

Single-ended, reference clock mode low-level input

VIL-SE

0.3 VDDA_33

voltage

VRX-CM-ACp

REFCLK+

VRX-CM-ACp = RMS(|VREFCLK+ + VREFCLK-|/2 VRX-CM-DC)

AC peak common mode

REFCLK–

140

VRX-CM-DC = DC(avg) of

input voltage

|VREFCLK+ + VREFCLK-|/2

REFCLK+

Differential and single-ended waveform input duty

Duty cycle

40%

60%

REFCLK–

cycle

ZC-DC

REFCLK+

Ω

REFCLK

± dc differential mode impedance

Clock source DC impedance

REFCLK–

(1)

The XIO2001 is compliant with the defined system jitter models for a PCI-Express reference clock and associated TX/RX link. Any

usage of the XIO2001 in a system configuration that does not conform to the defined system jitter models requires the system designer

to validate the system jitter budgets.

Electrical Characteristics

122

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