ST2202A datasheet(49/75 Pages) SITRONIX

49 / 75 page

ST2202A

Ver 2.5

49/75

9/16/2008

17.3 SPI Control/Status Registers

SPI control and status registers are summarized in TABLE 17-1.

TABLE 17-2 Summary Of SPI Control Registers

Address

Name

R/W

Bit 7/15 Bit 6/14 Bit 5/13 Bit 4/12 Bit 3/11 Bit 2/10

Bit 1/9

Bit 0/8

Default

$050

SDATAL

R/W

SD[7]

SD[6]

SD[5]

SD[4]

SD[3]

SD[2]

SD[1]

SD[0]

???? ????

$051

SDATAH

R/W

SD[15]

SD[14]

SD[13]

SD[12]

SD[11]

SD[10]

SD[9]

SD[8]

???? ????

$052

SCTR

R/W

SPIEN

RXIEN

ERIEN

MEREN

DRINV

POL

PHA

SMOD

0000 0000

$053

SCKR

R/W

SCK[2]

SCK[1]

SCK[0]

BC[3]

BC[2]

BC[1]

BC[0]

-000 0000

RXRDY TXEMP

SBZ

MDERR

OERR

BCERR

-000 -000

$054

SSR

Write any value to reset SSR

$00A

PCC

R/W

PCC[7]

PCC[6]

PCC[5]

PCC[4]

PCC[3]

PCC[2]

PCC[1]

PCC[0]

0000 0000

$00D

PFC

R/W

RXD0

TXD0

SRDY

MOSI

MISO

SCK

INTX

0000 0000

$03D

IREQH

R/W

IRURX

IRUTX

IRSRX

IRSTX

- - - - 0000

$03F

IENAH

R/W

IEURX

IEUTX

IESRX

IESTX

- - - - 0000

17.3.1 SPI Data Registers

TABLE 17-3 SPI Data Registers

Address

Name

R/W

Bit 7/15

Bit 6/14

Bit 5/13

Bit 4/12

Bit 3/11

Bit 2/10

Bit 1/9

Bit 0/8

Default

$050

SDATAL R/W

SD[7]

SD[6]

SD[5]

SD[4]

SD[3]

SD[2]

SD[1]

SD[0]

0000 0000

$051

SDATAH R/W

SD[15]

SD[14]

SD[13]

SD[12]

SD[11]

SD[10]

SD[9]

SD[8]

0000 0000

Bit

7~0: Write: Write low byte data to transmit buffer / clear status bit TXEMP / trigger an data exchange

Read: Read low byte data from receive buffer / clear status bit RXRDY

Bit 15~8:

Write: Write high byte data to transmit buffer / Read: Read high byte data from receive buffer

17.3.2 SPI Control Register

TABLE 17-4 SPI Control Register

Address Name

R/W

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default

$052

SCTR

R/W

SPIEN

RXIEN

ERIEN

MEREN

DRINV

POL

PHA

SMOD

0000 0000

Bit 7:

SPIEN : SPI control bit

0 = SPI disable

1 = SPI enable

Bit 6:

RXIEN : Receive buffer ready interrupt control bit

0 = Receive buffer ready interrupt disable

1 = Receive buffer ready interrupt enable

Bit 5:

ERIEN : Two error interrupts control bit

0 = Two error interrupts disable

1 = Two error interrupts enable

Bit 4:

MEREN : Mode fault detection control bit

0 = Mode fault detection disable

1 = Mode fault detection enable

Bit 3:

DRINV : DATA_READY active level selection bit

0 = Active level is high

1 = Active level is low

Bit 2~1: SPHA/SPOL : SPI clock polarity and phase control bits

Refer to section 17.1.1

Bit 0:

SMOD : Master / Slave modes selection bit

0 = Select slave mode

1 = Select master mode

ST2202A Datasheet(PDF) 49 Page - Sitronix Technology Co., Ltd.

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