ST2202A datasheet(25/75 Pages) SITRONIX

25 / 75 page

ST2202A

Ver 2.5

25/75

9/16/2008

2.. T

TIIM

R//E

T C

12.1 Prescaler

12.1.1 Function Description

The ST2202 has three timers, Base timer, Timer 0 and Timer 1,

and two prescalers PRES and PREW. There are two clock

sources, SYSCK and INTX, for PRES and one clock source,

CLK32, for PREW. Refer to FIGURE 12-1

TABLE 12-1 Summary of Timer Registers

Address Name

R/W

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default

$020

BTEN

R/W

BTEN[4] BTEN[3] BTEN[2] BTEN[1] BTEN[0]

- - -0 0000

$021

BTR

R/W

BTR[4]

BTR[3]

BTR[2]

BTR[1]

BTR[0]

- - -0 0000

PRS[7]

PRS[6]

PRS[5]

PRS[4]

PRS[3]

PRS[2]

PRS[1]

PRS[0]

0000 0000

$023

PRS

SRES

SENA

SENT

000 - - - - -

$024

T0M

R/W

T0M[5]

T0M[4]

T0M[2]

T0M[1]

T0M[0]

- -00

-000

$025

T0C

R/W

T0C[7]

T0C[6]

T0C[5]

T0C[4]

T0C[3]

T0C[2]

T0C[1]

T0C[0]

0000 0000

$026

T1M

R/W

T1M[4]

T1M[3]

T1M[2]

T1M[1]

T1M[0]

- - -0 0000

$027

T1C

R/W

T1C[7]

T1C[6]

T1C[5]

T1C[4]

T1C[3]

T1C[2]

T1C[1]

T1C[0]

0000 0000

XSEL

OSTP

XSTP

WSKP

WAIT

IRREN

HIGH

0000 0001

$030

SYS

XSEL

OSTP

XSTP

WSKP

WAIT

IRREN

LVDEN

0000 0000

$03C

IREQ

R/W

IRBT

IRPT

IRT1

IRT0

IRDAC

IRX

- -00 0000

$03E

IENA

R/W

IEBT

IEPT

IET1

IET0

IEDAC

IEX

- -00 0000

FIGURE 12-1 Structure Of Two Prescalers

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