ST2202A datasheet(23/75 Pages) SITRONIX

23 / 75 page

ST2202A

Ver 2.5

23/75

9/16/2008

TABLE 11-3 LCD Clock Control Register (LCKR)

Address Name

R/W

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default

$048

LCKR

LMOD

LCK[3]

LCK[2]

LCK[1]

LCK[0]

- - -0 0000

Bit 4:

LMOD : LCD data bus mode selection

0 = 1-bit mode

1 = 4-bit mode

Bit 3~0: LCKR[3:0] : LCD clock selection

LCDCK

LCKR[3:0]

1-bit mode

(LMOD=0)

4-bit mode

(LMOD=1)

0000

OSCK

0001

OSCK/2

0010

0011

OSCK

0100

0101

/10

0110

/12

0111

OSCK/2

/14

1000

/16

1001

/18

1010

/20

1011

OSCK/4

/22

1100

/24

1101

/26

1110

/28

1111

OSCK/6

/30

TABLE 11-4 PSG Control Register (PSGC)

Address Name

R/W

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default

PCK[2]

PCK[1]

PCK[0]

PRBS

C1EN

C0EN

DACE=0

-000 0000

$016

PSGC

R/W

PCK[2]

PCK[1]

PCK[0]

DMD[1]

DMD[0]

INH

DACE=1

-000 0000

Bit 3~0: PSGC[6:4] : PSG clock selection

PCK[2:0]

PSGCK

000

SYSCK/2

001

SYSCK/4

010

SYSCK/8

011

SYSCK/16

1xx

SYSCK

111

CLK32

TABLE 11-5 BGR Control Register (BCTR)

Address Name

R/W

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default

$063

BCTR

R/W

TEST

BSTR

BMOD

BGREN

0- - - -000

Bit 7: TEST : Test bit, must be “0”

Bit 2: BSTR : Modulation strength selection bit

0 = Full modulation strength (recommended)

1 = Half modulation strength

Bit 1: BMOD : Modulation mode selection bit

0 = Coarse modulation mode

1 = Fine modulation mode (recommended)

Bit 0: BGREN : BGR enable/disable bit

0 = Disable BGR

1 = Enable BGR

ST2202A Datasheet(PDF) 23 Page - Sitronix Technology Co., Ltd.

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