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ST7032 Datasheet(PDF) 46 Page - Sitronix Technology Co., Ltd. |
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ST7032 Datasheet(HTML) 46 Page - Sitronix Technology Co., Ltd. |
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46 / 63 page ![]() ST7032 V1.4 2008/08/18 46/61 l I2C interface SDA SCL tBUF tDH;STA tLOW tHD;DAT tHIGH tr tf tSU;DAT tSU;STO tSU;STA SDA ( Ta = 25 °C ) VDD=2.7 to 4.5V Rating VDD=4.5 to 5.5V Rating Item Signal Symbol Condition Min. Max. Min. Max. Units SCL clock frequency fSCLK DC 400 DC 400 KHz SCL clock low period tLOW 1.3 — 1.3 — SCL clock high period SCL tHIGH — 0.6 — 0.6 — us Data set-up time tSU;DAT 180 — 100 — ns Data hold time SI tHD:DAT — 0 0.9 0 0.9 us SCL,SDA rise time tr 20+0.1Cb 300 20+0.1Cb 300 SCL,SDA fall time SCL, SDA tf — 20+0.1Cb 300 20+0.1Cb 300 ns Capacitive load represent by each bus line Cb — — 400 — 400 pf Setup time for a repeated START condition tSU;STA — 0.6 — 0.6 — us Start condition hold time SI tHD;STA — 0.6 — 0.6 — us Setup time for STOP condition tSU;STO — 0.6 — 0.6 — us Bus free time between a Stop and START condition SCL tBUF — 1.3 — 1.3 — us |
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