ST7032 datasheet(7/63 Pages) SITRONIX

7 / 63 page

ST7032

V1.4

2008/08/18

7/61

n Pin Function

Name

Number

I/O Interfaced with

Function

XRESET

MPU

External reset pin. Only if the power on reset used, the

XRESET pin must be fixed to VDD.

Low active.

MPU

Select registers.

0: Instruction register (for write)

Busy flag & address counter (for read)

1: Data register (for write and read)

R/W

MPU

Select read or write (In parallel mode).

0: Write

1: Read

MPU

Starts data read/write. (

“E” must connect to “VDD” when

serial interface is selected.)

CSB

MPU

Chip select in parallel mode and serial interface (Low

active).When the CSB in falling edge state (in serial

interface), the shift register and the clock counter are reset.

Four high order bi-directional data bus pins. Used for data

transfer and receive between the MPU and the ST7032.

DB7 can be used as a busy flag. In serial interface mode

DB7 is SI (input data), DB6 is SCL (serial clock).

DB4 to DB7

I/O

MPU

In I

2C interface DB7 (SDA) is input data and DB6 (SCL) is

clock input.

SDA and SCL must connect to I

2C bus (I2C bus is to connect

a resister between SDA/SCL and the power of I

2C bus ).

DB0 to DB3

I/O

MPU

Four low order bi-directional data bus pins. Used for data

transfer and receive between the MPU and the ST7032.

These pins are not used during 4-bit operation.

Ext

ITO option

Extension instruction select:

0:enable extension instruction(add contrast/ICON/double

height font/ extension instruction)

1:disable extension instruction(compatible to ST7066U, but

without 5x11dot font)

PSB

MPU

Interface selection

0:serial mode

(

“E” must connect to “VDD” when serial mode is selected.)

1:parallel mode(4/8 bit)

In I

2C interface PSB must connect to VDD

PSI2B

ITO option

PSB

PSI2B

Interface

No use

SI4

SI2 (I

2C )

Parallel 68

Character generator select:

OPR1

OPR2

CGROM

CGRAM

240

250

248

OPR1,

OPR2

ITO option

256

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