| Electronic Components Datasheet Search |
|
ST7032 Datasheet(PDF) 13 Page - Sitronix Technology Co., Ltd. |
|
|
|||||||||||||||||||||||||||||
ST7032 Datasheet(HTML) 13 Page - Sitronix Technology Co., Ltd. |
|
13 / 63 page ![]() ST7032 V1.4 2008/08/18 13/61 During write operation, two 8-bit registers are used. One is data register (DR), the other is instruction register (IR). The data register (DR) is used as temporary data storage place for being written into DDRAM/CGRAM/ICON RAM, target RAM is selected by RAM address setting instruction. Each internal operation, writing into RAM, is done automatically. So to speak, after MPU writes data to DR, the data in DR is transferred into DDRAM/CGRAM/ICON RAM automatically. The Instruction register (IR) is used only to store instruction code transferred from MPU. MPU cannot use it to read instruction data. To select register, use RS input in I 2C interface. Table 2. Various kinds of operations according to RS and R/W bits. l Busy Flag (BF) When BF = "High ”, it indicates that the internal operation is being processed. So during this time the next instruction cannot be accepted. BF can be read, when RS = Low and R/W = High (Read Instruction Operation), through DB7 port. Before executing the next instruction, be sure that BF is not High. l Address Counter (AC) Address Counter (AC) stores DDRAM/CGRAM/ICON RAM address, transferred from IR. After writing into (reading from) DDRAM/CGRAM/ICON RAM, AC is automatically increased (decreased) by 1. When RS = "Low" and R/W = "High", AC can be read through DB0 ~ DB6 ports. RS R/W Operation L L Instruction Write operation (MPU writes Instruction code into IR) H L Data Write operation (MPU writes data into DR) S 0 1 1 11 1 R S 0 A control byte A data byte Co 0 R S A control byte A data byte A P Co slave address acknowledgement from ST7032i acknowledgement from ST7032i acknowledgement from ST7032i acknowledgement from ST7032i acknowledgement from ST7032i 2n>=0bytes command word n>=0bytes MSB.......................LSB 1 byte R/W Write mode 0 1 1 11 R / W slave address Co R S 00 0 0 00 control byte D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 data byte 1 0 1 0 Figure 5. 2-line Interface protocol 0 Last control byte to be sent. Only a stream of data bytes is allowed to follow. This stream may only be terminated by a STOP condition. Co 1 Another control byte will follow the data byte unless a STOP condition is received. |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |