ST7032 datasheet(12/63 Pages) SITRONIX

12 / 63 page

ST7032

V1.4

2008/08/18

12/61

2C Interface protocol

The ST7032 supports command, data write addressed slaves on the bus.

Before any data is transmitted on the I

2C Interface, the device, which should respond, is addressed first. Only one 7-bit

slave addresses (0111110) is reserved for the ST7032. The R/W is assigned to 0 for Write only.

The I

2C Interface protocol is illustrated in Fig.5.

The sequence is initiated with a START condition (S) from the I

2C Interface master, which is followed by the slave address.

All slaves with the corresponding address acknowledge in parallel, all the others will ignore the I

2C Interface transfer. After

acknowledgement, one or more command words follow which define the status of the addressed slaves.

A command word consists of a control byte, which defines Co and RS, plus a data byte.

The last control byte is tagged with a cleared most significant bit (i.e. the continuation bit Co). After a control byte with a

cleared Co bit, only data bytes will follow. The state of the RS bit defines whether the data byte is interpreted as a command

or as RAM data. All addressed slaves on the bus also acknowledge the control and data bytes. After the last control byte,

depending on the RS bit setting; either a series of display data bytes or command data bytes may follow. If the RS bit is set

to logic 1, these display bytes are stored in the display RAM at the address specified by the data pointer. The data pointer is

automatically updated and the data is directed to the intended ST7032i device. If the RS bit of the last control byte is set to

logic 0, these command bytes will be decoded and the setting of the device will be changed according to the received

commands. Only the addressed slave makes the acknowledgement after each byte. At the end of the transmission the I

INTERFACE-bus master issues a STOP condition (P).

DATA OUTPUT

BY TRANSMITTER

DATA OUTPUT

BY RECEIVER

SCL FROM

MASTER

START

condition

not acknowledge

acknowledge

clock pulse for

acknowledge ment

Figure 4. Acknowledgement on the 2-line Interface

ST7032 Datasheet(PDF) 12 Page - Sitronix Technology Co., Ltd.