ST7528 datasheet(21/97 Pages) SITRONIX

21 / 97 page

ST7528

Ver2.3

21/97

2007/1/3

FUNCTIONAL DESCRIPTION

MICROPROCESSOR INTERFACE

Chip Select Input

There is CSB pin for chip selection. The ST7528 can interface with an MPU when CSB is "L". When these pins are set to

any other combination, A0, E_RD, and RW_WR inputs are disabled and DB0 to DB7 are to be high impedance. And, in

case of serial interface, the internal shift register and the counter are reset.

Parallel / Serial Interface

ST7528 has five types of interface with an MPU, which are three serial and two parallel interfaces. This parallel or serial

interface is determined by PS pin as shown in Table 1.

Table 1 Parallel / Serial Interface Mode

Type

PS2

PS1

PS0

CSB

Interface mode

6800-series MPU mode

Parallel

CSB

8080-series MPU mode

CSB

3-Line SPI mode

CSB

4-Line SPI mode

Serial

CSB

IIC SPI mode

Parallel Interface (PS0 = "H")

The 8-bit bi-directional data bus is used in parallel interface and the type of MPU is selected by PS1 as shown in Table 2.

The type of data transfer is determined by signals at A0, E_RD and RW_WR as shown in Table 3.

Table 2 Microprocessor Selection for Parallel Interface

PS1

CSB

E_RD

RW_WR

DB0 to DB7

MPU bus

CSB

DB0 to DB7

6800-series

CSB

/RD

/WR

DB0 to DB7

8080-series

Table 3 Parallel Data Transfer

Common

6800-series

8080-series

E_RD

(E)

RW_WR

(RW)

E_RD

(/RD)

RW_WR

(/WR)

Description

Display data read out

Display data write

Writes to internal register (instruction)

NOTE: When E_RD pin is always pulled high for 6800-series interface, it can be used CSB for enable signal. In this case,

interface data is latched at the rising edge of CSB and the type of data transfer is determined by signals at A0, RW_WR as

in case of 6800-series mode.

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