SE97TP datasheet(27/55 Pages) NXP

27 / 55 page

SE97_7

Product data sheet

Rev. 07 — 29 January 2010

27 of 55

NXP Semiconductors

SE97

DDR memory module temp sensor with integrated SPD, 3.3 V

CTLB

Critical Trip Lock bit.

0 — Critical Alarm Trip register is not locked and can be altered (default)

1 — Critical Alarm Trip register settings cannot be altered

This bit is initially cleared. When set, this bit will return a ‘1’, and remains locked

until cleared by internal Power-on reset. This bit can be written with a single

write and do not require double writes.

AWLB

Alarm Window Lock bit.

0 — Upper and Lower Alarm Trip registers are not locked and can be altered

(default)

1 — Upper and Lower Alarm Trip registers setting cannot be altered

This bit is initially cleared. When set, this bit will return a ‘1’ and remains locked

until cleared by internal power-on reset. This bit can be written with a single write

and does not require double writes.

CEVNT

Clear EVENT (write only).

0 — no effect (default)

1 — clears active EVENT in Interrupt mode. Writing to this register has no

effect in Comparator mode.

When read, this register always returns zero.

ESTAT

EVENT Status (read only).

0 — EVENT output condition is not being asserted by this device (default)

1 — EVENT output pin is being asserted by this device due to Alarm Window

or Critical Trip condition

The actual event causing the EVENT can be determined from the Read

Temperature register. Interrupt Events can be cleared by writing to the ‘Clear

EVENT’ bit (CEVNT). Writing to this bit will have no effect.

EOCTL

EVENT Output Control.

0 — EVENT output disabled (default)

1 — EVENT output enabled

When either of the Critical Trip or Alarm Window lock bits is set, this bit cannot

be altered until unlocked.

CVO

Critical Event Only.

0 — EVENT output on Alarm or Critical temperature event (default)

1 — EVENT only if temperature is above the value in the critical temperature

When the Critical Trip or Alarm Window lock bit is set, this bit cannot be altered

until unlocked.

• Advisory note:

– JEDEC specification requires only the Alarm Window lock bit to be set.

– Work-around: Clear both Critical Trip and Alarm Window lock bits.

– Future 1.7 V to 3.6 V SE97B will require only the Alarm Window lock bit

to be set.

EVENT Polarity.

0 — active LOW (default)

1 — active HIGH. When either of the Critical Trip or Alarm Window lock bits is

set, this bit cannot be altered until unlocked.

Table 12.

Configuration register (address 01h) bit description …continued

Bit

Symbol

Description

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