SE97TP datasheet(17/55 Pages) NXP

17 / 55 page

SE97_7

Product data sheet

Rev. 07 — 29 January 2010

17 of 55

NXP Semiconductors

SE97

DDR memory module temp sensor with integrated SPD, 3.3 V

7.10 EEPROM operation

The 2-kbit EEPROM is organized as either 256 bytes of 8 bits each (byte mode), or

16 pages of 16 bytes each (page mode). Accessing the EEPROM in byte mode or page

mode is automatic; partial page write of 2 bytes, 4 bytes, or 8 bytes is also supported.

Communication with the EEPROM is via the 2-wire serial I2C-bus or SMBus. Figure 14

provides an overview of the EEPROM partitioning.

The EEPROM can be read over voltage range 1.7 V to 3.6 V, but all write operations must

be done 3.0 V to 3.6 V.

7.10.1 Write operations

7.10.1.1

Byte Write

In Byte Write mode the master creates a START condition and then broadcasts the slave

address, byte address, and data to be written. The slave acknowledges all 3 bytes by

pulling down the SDA line during the ninth clock cycle following each byte. The master

creates a STOP condition after the last ACK from the slave, which then starts the internal

write operation (see Figure 15). During internal write, the slave will ignore any read/write

request from the master.

Fig 14. EEPROM partitioning

FFh

80h

7Fh

0Fh

00h

00h 01h

07h

…

1 page

or 16 bytes

8 pages or

128 bytes

16 pages or

256 bytes

no write protect

write protect

by software

002aac812

Fig 15. Byte Write timing

002aab246

A2 A1 A0

slave address (memory)

START condition

R/W acknowledge

from slave

acknowledge

from slave

word address

SDA

STOP condition;

write to the memory is performed

data

DATA

acknowledge

from slave

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