SE97TP datasheet(28/55 Pages) NXP

28 / 55 page

SE97_7

Product data sheet

Rev. 07 — 29 January 2010

28 of 55

NXP Semiconductors

SE97

DDR memory module temp sensor with integrated SPD, 3.3 V

EMD

EVENT Mode.

0 — comparator output mode (default)

1 — interrupt mode

When either of the Critical Trip or Alarm Window lock bits is set, this bit cannot

be altered until unlocked.

Table 12.

Configuration register (address 01h) bit description …continued

Bit

Symbol

Description

Table 13.

Hysteresis enable

Action

Below Alarm Window bit (bit 13)

Above Alarm Window bit (bit 14)

Above Critical Trip bit (bit 15)

Temperature

slope

Threshold

temperature

Temperature

slope

Threshold

temperature

Temperature

slope

Threshold

temperature

sets

falling

Ttrip(l) − Thys

rising

Ttrip(u)

rising

Tth(crit)

clears

rising

Ttrip(l)

falling

Ttrip(u) − Thys

falling

Tth(crit) − Thys

Fig 22. Hysteresis: how it works

002aac799

current temperature

time

temperature

set

clear

set

clear

set

clear

Below Alarm Window

(register 05h;

bit 13 = BAW bit)

Above Alarm Window

(register 05h;

bit 14 = AAW bit)

Above Critical Trip

(register 05h;

bit 15 = ACT bit)

lower alarm

threshold

upper alarm

threshold

critical alarm

threshold

hysteresis

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