SE97TP datasheet(34/55 Pages) NXP

34 / 55 page

SE97_7

Product data sheet

Rev. 07 — 29 January 2010

34 of 55

NXP Semiconductors

SE97

DDR memory module temp sensor with integrated SPD, 3.3 V

8.9 SMBus register

Table 25.

SMBus Time-out register bit allocation

Bit

Symbol

RFU

Default

0000000

Access

RRRRR

Bit

Symbol

STMOUT

RFU

SALRT

Default

0000000

Access

R/W

RRRRRR

R/W

Table 26.

SMBus Time-out register bit description

Bit

Symbol

Description

15:8

RFU

reserved; always ‘0’

STMOUT

SMBus time-out.

0 — SMBus time-out is enabled (default)

1 — disable SMBus time-out

When either of the Critical Trip or Alarm Window lock bits is set, this bit

cannot be altered until unlocked.

6:1

RFU

reserved; always ‘0’

SALRT

SMBus ALERT Response Address (ARA).

0 — SMBus ARA is enabled (default)

1 — disable SMBus ARA

When either of the Critical Trip or Alarm Window lock bits is set, this bit

cannot be altered until unlocked.

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