MAX793_EPE datasheet(7/20 Pages) MAXIM

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3.0V/3.3V Adjustable Microprocessor

Supervisory Circuits

_______________________________________________________________________________________

______________________________________________________________Pin Description

Supply Output for CMOS RAM. When VCC rises above the reset threshold or above

VBATT, OUT is connected to VCC through an internal p-channel MOSFET switch. When

VCC falls below VSW and VBATT, BATT connects to OUT.

OUT

Reset Input. Connect to an external resistor-divider to select the reset threshold. The

reset threshold can be programmed anywhere in the VSW to 5.5V range.

RESET IN

(MAX794)

—

Battery Status Output. High in normal operating mode when VBATT exceeds VBOK, other-

wise low. VBATT is checked continuously. Disabled and logic low while VCC is below VSW.

BATT OK

(MAX793)

Main Supply Input

VCC

Power-Fail Comparator Output. When PFI is less than VPFT or when VCC falls below

VSW, PFO goes low; otherwise, PFO remains high. PFO is also used to enable the bat-

tery freshness seal (see

Battery Freshness Seal, and Power-Fail Comparator sections).

PFO

—

Active-High Reset Output. Sources and sinks current. RESET is the inverse of RESET.

RESET

Chip-Enable Output. CE OUT goes low only when CE IN is low and reset is not asserted.

If CE IN is low when reset is asserted, CE OUT remains low for 10µs or until CE IN goes

high, whichever occurs first. CE OUT is pulled up to OUT.

CE OUT

—

Ground

GND

Power-Fail Comparator Input. When PFI is less than VPFT or when VCC falls below VSW,

PFO goes low; otherwise, PFO remains high (see Power-Fail Comparator section).

Connect to VCC if unused.

PFI

Chip-Enable Input. The input to the chip-enable gating circuit. Connect to GND if unused.

CE IN

—

Watchdog Output. WDO goes low if WDI remains either high or low for longer than the

watchdog timeout period. WDO returns high on the next transition of WDI. WDO is a

logic high for VSW < VCC < VRST, and low when VCC is below VSW.

WDO

—

Manual Reset Input. A logic low on MR asserts reset. Reset remains asserted as long as

MR is low and for 200ms after MR returns high. The active-low input has an internal

70µA pullup current. It can be driven from a TTL- or CMOS-logic line or shorted to

ground with a switch. Leave open if unused.

—

Watchdog Input. If WDI remains either high or low for longer than the watchdog timeout

period, the internal watchdog timer runs out and WDO goes low. WDO returns high on

the next transition of WDI. Connect WDO to MR to generate a reset due to a watchdog

fault.

WDI

—

Early Power-Fail Warning Output. Low when VCC falls to VLR. This output can be used to

generate an NMI to provide early warning of imminent power failure.

LOWLINE

—

Open-Drain, Active-Low Reset Output. Pulses low for 200ms when triggered, and stays

low whenever VCC is below the reset threshold or when MR is a logic low. It remains low

for 200ms after either VCC rises above the reset threshold, the watchdog triggers a reset

(WDO connected to MR), or MR goes low to high.

RESET

Backup-Battery Input. When VCC falls below VSW and VBATT, OUT switches from VCC to

BATT. When VCC rises above the reset threshold or above VBATT, OUT reconnects to

VCC. VBATT can exceed VCC. Connect VCC, OUT, and BATT together if no battery is

used.

BATT

Logic Output/External Bypass Switch-Driver Output. High when OUT switches to BATT.

Low when OUT switches to VCC. Connect the base/gate of PNP/PMOS transistor to

BATT ON for IOUT requirements exceeding 75mA.

BATT ON

MAX793/

MAX794

FUNCTION

NAME

MAX795

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