__________Applications Information

These µP supervisory circuits are not short-circuit pro-

transients such as charging a decoupling capacitor,

pins to ground by placing 0.1µF ceramic capacitors as

close to the device as possible.

Driving an External Switch with BATT ON

BATT ON can be directly connected to the base of a

PNP transistor or the gate of a PMOS transistor. The

PNP connection is straightforward: connect the emitter

(Figure 14a). No current-limiting resistor is required, but

a resistor connecting the base of the PNP to BATT ON

longing battery life in portable equipment.

If you are using a PMOS transistor, however, it must be

connected backwards from the traditional method.

the source to OUT (Figure 14b). This method orients

backup battery from discharging through the FET when

its gate is high. Two PMOS transistors in the Siliconix

-2.7V. The Si9433DY has a maximum 100m

Ω drain-

source on-resistance with 2.7V of gate drive and a 2A

drain-source current. The Si9434DY specifies a 60m

Ω

drain-source on-resistance with 2.7V of gate drive and

a 5.1A drain-source current.

Using a Super Cap as a Backup

Power Source

Super caps are capacitors with extremely high capaci-

tance values (e.g., order of 0.47F) for their size. Figure

15 shows two ways to use a super cap as a backup

power source. The super cap can be connected

through a diode to the 3V input (Figure 15a); or, if a 5V

supply is also available, the super cap can be charged

up to the 5V supply (Figure 15b), allowing a longer

precautions when using these µP supervisors with a

super cap.

Operation without a

Backup Power Source

These µP supervisors were designed for battery-

backed applications. If a backup battery is not used,

ent µP supervisor. See the

µP Supervisory Circuits table

at the end of this data sheet.

Replacing the Backup Battery

remains valid, without danger of triggering a reset

pulse, provided that BATT is decoupled with a 0.1µF

reset threshold, battery-backup mode cannot be

entered.

3.0V/3.3V Adjustable Microprocessor

Supervisory Circuits

______________________________________________________________________________________

15

CE IN

High impedance

CE OUT

Pulled to BATT

RESET

Logic low

BATT

Connected to OUT

LOWLINE

Logic low

RESET

WDO

Logic low

WDI

Disabled

BATT OK

Logic low

PFO

Logic low

MR

PFI

Disabled

Disconnected from OUT

BATT ON

Pulled up to BATT

OUT

Connected to BATT through an internal

140

Ω switch

PIN NAME

STATUS

Table 1. Input and Output Status in

Battery-Backup Mode

3.3V

3.6V

3.3V

3.6V

Figure 13. Battery Switchover Timing

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