LPC3230 datasheet(36/73 Pages) NXP

36 / 73 page

LPC3220_30_40_50_1

Preliminary data sheet

Rev. 01 — 6 February 2009

36 of 73

NXP Semiconductors

LPC3220/30/40/50

16/32-bit ARM microcontrollers

There is a separate slave transmit FIFO. The slave transmit FIFO (TXS) and its level are

only available when the controller is conﬁgured as a Master/Slave device and is operating

in a multi-master environment. Separate TX FIFOs are needed in a multi-master because

a controller might have a message queued for transmission when an external master

addresses it to be come a slave-transmitter, a second source of data is needed.

Note that the I2C clock must be enabled in the I2CCLK_CTRL register before using the

I2C. The I2C clock can be disabled between communications, if used as a single master

I2C-bus interface, software has full control of when I2C communication is taking place on

the bus.

7.8.4.1

Features

• The two I2C-bus blocks are standard I2C-bus compliant interfaces that may be used in

Single-master, Multi-master or Slave modes.

• Programmable clock to allow adjustment of I2C-bus transfer rates.

• Bidirectional data transfer.

• Serial clock synchronization allows devices with different bit rates to communicate via

one serial bus.

• Serial clock synchronization can be used as a handshake mechanism to suspend and

resume serial transfer.

7.8.5 I2S-bus audio controller

The I2S-bus provides a standard communication interface for digital audio applications

The I2S-bus speciﬁcation deﬁnes a 3-wire serial bus using one data line, one clock line,

and one word select signal. Each I2S connection can act as a master or a slave. The

master connection determines the frequency of the clock line and all other slaves are

driven by this clock source. The two I2S-bus interfaces on the LPC3220/30/40/50 provides

a separate transmit and receive channel, providing a total of two transmit channels and

two receive channels. Each I2S channel supports monaural or stereo formatted data.

7.8.5.1

Features

• The interface has separate input/output channels each of which can operate in master

or slave mode.

• Capable of handling 8-bit, 16-bit, and 32-bit word sizes.

• Mono and stereo audio data supported.

• Supports standard sampling frequencies (8 kHz, 11.025 kHz, 16 kHz, 22.05 kHz,

32 kHz, 44.1 kHz, 48 kHz, 96 kHz).

• Word select period can be conﬁgured in master mode (separately for I2S input and

output).

• Two 8 word FIFO data buffers are provided, one for transmit and one for receive.

• Generates interrupt requests when buffer levels cross a programmable boundary.

• Two DMA requests, controlled by programmable buffer levels. These are connected to

the GPDMA block.

• Controls include reset, stop, and mute options separately for I2S input and I2S output.

LPC3230 Datasheet(PDF) 36 Page - NXP Semiconductors

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