56F807 datasheet(32/60 Pages) FREESCALE

Part #	56F807

Description	16-bit Digital Signal Controllers

PDF	60 Pages

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Manufacturer	FREESCALE [Freescale Semiconductor, Inc]

Direct Link	http://www.freescale.com

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56F807 Technical Data Technical Data, Rev. 16

Freescale Semiconductor

3.4.4

Phase Locked Loop Timing

Table 3-9 PLL Timing

Operating Conditions: V

SS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C

Characteristic

Symbol

Min

Typ

Max

Unit

External reference crystal frequency for the PLL1

An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work

correctly. The PLL is optimized for 8MHz input crystal.2.

fosc

MHz

PLL output frequency2

ZCLK may not exceed 80MHz. For additional information on ZCLK and fout/2, please refer to the OCCS chapter in the

User Manual. ZCLK = fop

fout/2

—

110

MHz

PLL stabilization time3 0o to +85oC

This is the minimum time required after the PLL set-up is changed to ensure reliable operation.

tplls

—1

PLL stabilization time3 -40o to 0oC

tplls

—

100

200

56F807 Datasheet(PDF) 32 Page - Freescale Semiconductor, Inc