56F807 datasheet(45/60 Pages) FREESCALE

45 / 60 page

Controller Area Network (CAN) Timing

56F807 Technical Data Technical Data, Rev. 16

Freescale Semiconductor

Parasitic capacitance due to package, pin to pin, and pin to package base coupling. (1.8pf)

Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing. (2.04pf)

Equivalent resistance for the ESD isolation resistor and the channel select mux. (500 ohms)

Sampling capacitor at the sample and hold circuit. Capacitor 4 is normally disconnected from the input and is only connected to it at

sampling time. (1pf)

Figure 3-27 Equivalent Analog Input Circuit

3.12 Controller Area Network (CAN) Timing

Figure 3-28 Bus Wakeup Detection

Table 3-17 CAN Timing2

Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL < 50pF, MSCAN Clock = 30MHz

Characteristic

Symbol

Min

Max

Unit

Baud Rate

BRCAN

—

1Mbps

Bus Wakeup detection 1

If Wakeup glitch filter is enabled during the design initialization and also CAN is put into SLEEP mode then, any bus event

(on MSCAN_RX pin) whose duration is less than 5 microseconds is filtered away. However, a valid CAN bus wakeup detection

takes place for a wakeup pulse equal to or greater than 5 microseconds. The number 5 microseconds originates from the fact

that the CAN wakeup message consists of 5 dominant bits at the highest possible baud rate of 1Mbps.

Parameters listed are guaranteed by design

T WAKEUP

—

μs

ADC analog input

T WAKEUP

MSCAN_RX

CAN receive

data pin

(Input)

56F807 Datasheet(PDF) 45 Page - Freescale Semiconductor, Inc