56F807 datasheet(35/60 Pages) FREESCALE

35 / 60 page

Reset, Stop, Wait, Mode Select, and Interrupt Timing

56F807 Technical Data Technical Data, Rev. 16

Freescale Semiconductor

3.6 Reset, Stop, Wait, Mode Select, and Interrupt Timing

Table 3-11 Reset, Stop, Wait, Mode Select, and Interrupt Timing1,5

Operating Conditions: V

SS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF

In the formulas, T = clock cycle. For an operating frequency of 80MHz, T = 12.5ns.

Characteristic

Symbol

Min

Max

Unit

See Figure

RESET Assertion to Address, Data and Control Signals

High Impedance

tRAZ

—21

3-12

Minimum RESET Assertion Duration2

OMR Bit 6 = 0

OMR Bit 6 = 1

Circuit stabilization delay is required during reset when using an external clock or crystal oscillator in two cases:

• After power-on reset

• When recovering from Stop state

tRA

275,000T

128T

—

3-12

RESET Deassertion to First External Address Output

tRDA

33T

34T

3-12

Edge-sensitive Interrupt Request Width

tIRW

1.5T

—

3-13

IRQA, IRQB Assertion to External Data Memory Access

Out Valid, caused by first instruction execution in the

interrupt service routine

tIDM

15T

—

3-14

IRQA, IRQB Assertion to General Purpose Output Valid,

caused by first instruction execution in the interrupt

service routine

tIG

16T

—

3-14

IRQA Low to First Valid Interrupt Vector Address Out

recovery from Wait State3

The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state. This is

not the minimum required so that the IRQA interrupt is accepted.

tIRI

13T

—

3-15

IRQA Width Assertion to Recover from Stop State4

The interrupt instruction fetch is visible on the pins only in Mode 3.

Parameters listed are guaranteed by design.

tIW

—

3-16

Delay from IRQA Assertion to Fetch of first instruction

(exiting Stop)

OMR Bit 6 = 0

OMR Bit 6 = 1

tIF

—

275,000T

12T

3-16

Duration for Level Sensitive IRQA Assertion to Cause

the Fetch of First IRQA Interrupt Instruction (exiting Stop)

OMR Bit 6 = 0

OMR Bit 6 = 1

tIRQ

—

275,000T

12T

3-17

Delay from Level Sensitive IRQA Assertion to First

Interrupt Vector Address Out Valid (exiting Stop)

OMR Bit 6 = 0

OMR Bit 6 = 1

tII

—

275,000T

12T

3-17

56F807 Datasheet(PDF) 35 Page - Freescale Semiconductor, Inc

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