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56F807 Datasheet(PDF) 42 Page - Freescale Semiconductor, Inc |
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56F807 Datasheet(HTML) 42 Page - Freescale Semiconductor, Inc |
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42 / 60 page ![]() 56F807 Technical Data Technical Data, Rev. 16 42 Freescale Semiconductor 3.9 Quadrature Decoder Timing Figure 3-24 Quadrature Decoder Timing Table 3-14 Quadrature Decoder Timing1, 2 Operating Conditions: V SS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF, fOP = 80MHz 1. In the formulas listed, T = the clock cycle. For 80MHz operation, T=12.5ns. VSS = 0V, VDD = 3.0–3.6V, TA = –40° to +85°C, CL ≤ 50pF. 2. Parameters listed are guaranteed by design. Characteristic Symbol Min Max Unit Quadrature input period PIN 8T + 12 — ns Quadrature input high/low period PHL 4T + 6 — ns Quadrature phase period PPH 2T + 3 — ns Phase B (Input) PIN PHL PHL Phase A (Input) PIN PHL PHL PPH PPH PPH PPH |
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