LPC1313 datasheet(24/62 Pages) NXP

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LPC1311_13_42_43

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Product data sheet

Rev. 3 — 10 August 2010

24 of 62

NXP Semiconductors

LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

7.17.1.1

Internal RC oscillator

The IRC may be used as the clock source for the WDT, and/or as the clock that drives the

system PLL and subsequently the CPU. The nominal IRC frequency is 12 MHz. The IRC

is trimmed to 1 % accuracy over the entire voltage and temperature range.

Upon power-up, any chip reset, or wake-up from Deep power-down mode, the

LPC1311/13/42/43 use the IRC as the clock source. Software may later switch to one of

the other available clock sources.

7.17.1.2

System oscillator

The system oscillator can be used as the clock source for the CPU, with or without using

the PLL. On the LPC134x, the system oscillator must be used to provide the clock source

to USB.

The system oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be

boosted to a higher frequency, up to the maximum CPU operating frequency, by the

system PLL.

7.17.1.3

Watchdog oscillator

The watchdog oscillator can be used as a clock source that directly drives the CPU, the

watchdog timer, or the CLKOUT pin. The watchdog oscillator nominal frequency is

programmable between 7.8 kHz and 1.7 MHz. The frequency spread over processing and

temperature is

±40 % (see also Table 14).

7.17.2 System PLL and USB PLL

The LPC134x contain a system PLL and a dedicated PLL for generating the 48 MHz USB

clock. The LPC131x contain the system PLL only. The system and USB PLLs are

identical.

The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input

frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO).

The multiplier can be an integer value from 1 to 32. The CCO operates in the range of

156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO within

its frequency range while the PLL is providing the desired output frequency. The output

divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. Since the

minimum output divider value is 2, it is insured that the PLL output has a 50 % duty cycle.

The PLL is turned off and bypassed following a chip reset and may be enabled by

software. The program must configure and activate the PLL, wait for the PLL to lock, and

then connect to the PLL as a clock source. The PLL settling time is 100

μs.

7.17.3 Clock output

The LPC1311/13/42/43 features a clock output function that routes the IRC oscillator, the

system oscillator, the watchdog oscillator, or the main clock to an output pin.

7.17.4 Wake-up process

The LPC1311/13/42/43 begin operation at power-up and when awakened from Deep

power-down mode by using the 12 MHz IRC oscillator as the clock source. This allows

chip operation to resume quickly. If the main oscillator or the PLL is needed by the

application, software will need to enable these features and wait for them to stabilize

before they are used as a clock source.

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