LPC1313 datasheet(27/62 Pages) NXP

27 / 62 page

LPC1311_13_42_43

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Product data sheet

Rev. 3 — 10 August 2010

27 of 62

NXP Semiconductors

LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

7.18.5 Boot loader

The boot loader controls initial operation after reset and also provides the means to

program the flash memory. This could be initial programming of a blank device, erasure

and re-programming of a previously programmed device, or programming of the flash

memory by the application program in a running system.

The boot loader code is executed every time the part is reset or powered up. The loader

can either execute the ISP command handler or the user application code, or, on the

LPC134x, it can program the flash image via an attached MSC device through USB

(Windows operating system only). A LOW level during reset applied to the PIO0_1 pin is

considered as an external hardware request to start the ISP command handler or the USB

device enumeration. The state of PIO0_3 determines whether the UART or USB interface

will be used (LPC134x only).

7.18.6 APB interface

The APB peripherals are located on one APB bus.

7.18.7 AHB-Lite

The AHB-Lite connects the instruction (I-code) and data (D-code) CPU buses of the ARM

Cortex-M3 to the flash memory, the main static RAM, and the boot ROM.

7.18.8 External interrupt inputs

All GPIO pins can be level or edge sensitive interrupt inputs. In addition, start logic inputs

serve as external interrupts (see Section 7.18.1).

7.18.9 Memory mapping control

The Cortex-M3 incorporates a mechanism that allows remapping the interrupt vector table

to alternate locations in the memory map. This is controlled via the Vector Table Offset

The vector table may be located anywhere within the bottom 1 GB of Cortex-M3 address

space. The vector table must be located on a 256 word boundary.

7.19 Emulation and debugging

Debug functions are integrated into the ARM Cortex-M3. Serial wire debug is supported.

LPC1313 Datasheet(PDF) 27 Page - NXP Semiconductors