LPC1313 datasheet(46/62 Pages) NXP

46 / 62 page

LPC1311_13_42_43

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 10 August 2010

46 of 62

NXP Semiconductors

LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

10.6 SSP interface

[1]

Tcy(clk) = (SSPCLKDIV

× (1 + SCR) × CPSDVSR) / fmain. The clock cycle time derived from the SPI bit rate Tcy(clk) is a function of the

main clock frequency fmain, the SSP peripheral clock divider (SSPCLKDIV), the SSP SCR parameter (specified in the SSP0CR0

[2]

Tamb =

−40 °C to +85 °C.

[3]

Tcy(clk) = 12

× Tcy(PCLK).

[4]

Tamb = 25

°C; VDD = 3.3 V.

Table 17.

Dynamic characteristics: SSP pins in SPI mode

Symbol

Parameter

Conditions

Min

Max

Unit

SSP master

Tcy(clk)

clock cycle time

when only receiving

[1]

when only transmitting [1]

27.8

tDS

data set-up time

in SPI mode;

2.4 V

≤ VDD ≤ 3.6 V

[2]

2.0 V

≤ VDD < 2.4 V [2]

tDH

data hold time

in SPI mode

[2]

tv(Q)

data output valid time

in SPI mode

[2]

-10

th(Q)

data output hold time

in SPI mode

[2]

SSP slave

Tcy(PCLK)

PCLK cycle time

13.9

tDS

data set-up time

in SPI mode

[3][4]

tDH

data hold time

in SPI mode

[3][4]

× Tcy(PCLK) + 4

tv(Q)

data output valid time

in SPI mode

[3][4]

-3

× Tcy(PCLK) + 11

th(Q)

data output hold time

in SPI mode

[3][4]

-2

× Tcy(PCLK) + 5

LPC1313 Datasheet(PDF) 46 Page - NXP Semiconductors

LPC1313 Datasheet(HTML) 46 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62

Datasheet Download

Link URL