LPC1313 datasheet(16/62 Pages) NXP

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LPC1311_13_42_43

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Product data sheet

Rev. 3 — 10 August 2010

16 of 62

NXP Semiconductors

LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

Functional description

7.1 Architectural overview

The ARM Cortex-M3 includes three AHB-Lite buses: the system bus, the I-code bus, and

the D-code bus (see Figure 1). The I-code and D-code core buses are faster than the

system bus and are used similarly to TCM interfaces: one bus dedicated for instruction

fetch (I-code) and one bus for data access (D-code). The use of two core buses allows for

simultaneous operations if concurrent operations target different devices.

7.2 ARM Cortex-M3 processor

The ARM Cortex-M3 is a general purpose, 32-bit microprocessor, which offers high

performance and very low power consumption. The ARM Cortex-M3 offers many new

features, including a Thumb-2 instruction set, low interrupt latency, hardware divide,

interruptible/continuable multiple load and store instructions, automatic state save and

restore for interrupts, tightly integrated interrupt controller, and multiple core buses

capable of simultaneous accesses.

Pipeline techniques are employed so that all parts of the processing and memory systems

can operate continuously. Typically, while one instruction is being executed, its successor

is being decoded, and a third instruction is being fetched from memory.

The ARM Cortex-M3 processor is described in detail in the Cortex-M3 Technical

Reference Manual which is available on the official ARM website.

7.3 On-chip flash program memory

The LPC1311/13/42/43 contain 32 kB (LPC1313 and LPC1343), 16 kB (LPC1342), or

8 kB (LPC1311) of on-chip flash memory.

7.4 On-chip SRAM

The LPC1311/13/42/43 contain a total of 8 kB (LPC1343 and LPC1313) or 4 kB (LPC1342

and LPC1311) on-chip static RAM memory.

7.5 Memory map

The LPC134x incorporates several distinct memory regions, shown in the following

figures. Figure 6 shows the overall map of the entire address space from the user

program viewpoint following reset. The interrupt vector area supports address remapping.

The AHB peripheral area is 2 MB in size and is divided to allow for up to 128 peripherals.

The APB peripheral area is 512 kB in size and is divided to allow for up to 32 peripherals.

Each peripheral of either type is allocated 16 kB of space. This allows simplifying the

address decoding for each peripheral.

LPC1313 Datasheet(PDF) 16 Page - NXP Semiconductors