AD5433 datasheet(4/32 Pages) AD

4 / 32 page

AD5424/AD5433/AD5445

Rev. B | Page 4 of 32

Parameter

Min

Typ

Max

Unit

Conditions

Output Capacitance

IOUT1

All 0s loaded

All 1s loaded

IOUT2

All 0s loaded

All 1s loaded

Digital Feedthrough

nV-s

Feedthrough to DAC output with CS high and

alternate loading of all 0s and all 1s

Analog THD

VREF = 3.5 V p-p, all 1s loaded, f = 100 kHz

Digital THD

Clock = 10 MHz, VREF = 3.5 V

50 kHz fOUT

Output Noise Spectral Density

nV√Hz

@ 1 kHz

SFDR Performance (Wide Band)

AD5445, VREF = 3.5 V

Clock = 10 MHz

500 kHz fOUT

100 kHz fOUT

50 kHz fOUT

Clock = 25 MHz

500 kHz fOUT

100 kHz fOUT

50 kHz fOUT

SFDR Performance (Narrow Band)

AD5445, VREF = 3.5 V

Clock = 10 MHz

500 kHz fOUT

100 kHz fOUT

50 kHz fOUT

Clock = 25 MHz

500 kHz fOUT

100 kHz fOUT

50 kHz fOUT

Intermodulation Distortion

AD5445, VREF = 3.5 V

Clock = 10 MHz

f1 = 400 kHz, f2 = 500 kHz

f1 = 40 kHz, f2 = 50 kHz

Clock = 25 MHz

f1 = 400 kHz, f2 = 500 kHz

f1 = 40 kHz, f2 = 50 kHz

POWER REQUIREMENTS

Power Supply Range

2.5

5.5

IDD

0.6

μA

TA = 25°C, logic inputs = 0 V or VDD

0.4

μA

Logic inputs = 0 V or VDD, T= −40°C to +125°C

Power Supply Sensitivity

0.001

%/%

ΔVDD = ±5%

1 Guaranteed by design, not subject to production test.

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