AD5433 datasheet(22/32 Pages) AD

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AD5424/AD5433/AD5445

Rev. B | Page 22 of 32

Provided the DAC switches are driven from true wideband low

impedance sources (VIN and AGND), they settle quickly. Conse-

quently, the slew rate and settling time of a voltage switching

DAC circuit is determined largely by the output op amp. To

obtain minimum settling time in this configuration, it is impor-

tant to minimize capacitance at the VREF node (voltage output

node in this application) of the DAC. This is done by using low

inputs capacitance buffer amplifiers and careful board design.

Most single-supply circuits include ground as part of the analog

signal range, which in turns requires an amplifier that can

handle rail-to-rail signals. There is a large range of single-supply

amplifiers available from Analog Devices.

PARALLEL INTERFACE

Data is loaded to the AD5424/AD5433/AD5445 in the format

of an 8-, 10-, or 12-bit parallel word. Control lines CS and R/W

allow data to be written to or read from the DAC register. A

write event takes place when CS and R/W are brought low, data

available on the data lines fills the shift register, and the rising

edge of CS latches the data and transfers the latched data-word

to the DAC register. The DAC latches are not transparent, thus

a write sequence must consist of a falling and rising edge on CS

to ensure that data is loaded to the DAC register and its analog

equivalent is reflected on the DAC output.

A read event takes place when R/W is held high and CS is

brought low. New data is loaded from the DAC register back to

the input register and out onto the data line where it can be read

back to the controller for verification or diagnostic purposes.

MICROPROCESSOR INTERFACING

ADSP-21xx-to-AD5424/AD5433/AD5445 Interface

Figure 56 shows the AD5424/AD5433/AD5445 interfaced to

the ADSP-21xx series of DSPs as a memory-mapped device. A

single wait state may be necessary to interface the AD5424/

AD5433/AD5445 to the ADSP-21xx, depending on the clock

speed of the DSP. The wait state can be programmed via the

data memory wait state control register of the ADSP-21xx (see

the ADSP-21xx family user’s manual for details).

R/W

DB0 TO DB11

AD5424/

AD5433/

AD5445*

ADDRESS

DECODER

DATA 0 TO

DATA 23

ADDRESS BUS

ADDR0 TO

ADRR13

ADSP-21xx*

DATA BUS

DMS

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 56. ADSP21xx-to-AD5424/AD5433/AD5445 Interface

8xC51-to-AD5424/AD5433/AD5445 Interface

Figure 57 shows the interface between the AD5424/AD5433/

AD5445 and the 8xC51 family of DSPs. To facilitate external

data memory access, the address latch enable (ALE) mode is

enabled. The low byte of the address is latched with this output

pulse during access to external memory. AD0 to AD7 are the

multiplexed low order addresses and data bus and require

strong internal pull-ups when emitting 1s. During access to

external memory, A8 to A15 are the high order address bytes.

Since these ports are open drained, they also require strong

internal pull-ups when emitting 1s.

R/W

DB0 TO DB11

AD5424/

AD5433/

AD5445*

ADDRESS

DECODER

AD0 TO AD7

ADDRESS BUS

A8 TO A15

8051*

DATA BUS

*ADDITIONAL PINS OMITTED FOR CLARITY

8-BIT

LATCH

ALE

Figure 57. 8xC51-to-AD5424/AD5433/AD5445 Interface

ADSP-BF5xx-to-AD5424/AD5433/AD5445 Interface

Figure 58 shows a typical interface between the AD5424/

AD5433/AD5445 and the ADSP-BF5xx family of DSPs. The

asynchronous memory write cycle of the processor drives the

digital inputs of the DAC. The AMSx line is actually four

memory select lines. Internal ADDR lines are decoded into

AMS3-0 , these lines are then inserted as chip selects. The rest of

the interface is a standard handshaking operation.

R/W

DB0 TO DB11

AD5424/

AD5433/

AD5445*

ADDRESS

DECODER

DATA 0 TO

DATA 23

ADDRESS BUS

ADDR1 TO

ADRR19

ADSP-BF5xx

DATA BUS

AMSx

AWE

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 58. ADSP-BF5xx-to-AD5424/AD5433/AD5445 Interface

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