AD5433 datasheet(18/32 Pages) AD

18 / 32 page

AD5424/AD5433/AD5445

Rev. B | Page 18 of 32

VREF

±10V

VDD

R/W

20k

10k

20k

IOUT1

IOUT2

RFB

GND

AGND

DATA

INPUTS

VOUT =–VREF TO +VREF

AD5424/

AD5433/

AD5445

R1 AND R2 ARE USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.

ADJUST R1 FOR VOUT = 0V WITH CODE 10000000 LOADED TO DAC.

MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS R3 AND R4.

C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED IF A1/A2 IS

A HIGH SPEED AMPLIFIER.

NOTES:

VREF

Figure 50. Bipolar Operation (4-Quadrant Multiplication)

BIPOLAR OPERATION

In some applications, it may be necessary to generate full

4-quadrant multiplying operation or a bipolar output swing.

This can be easily accomplished by using another external

amplifier and some external resistors, as shown in Figure 50. In

this circuit, the second amplifier, A2, provides a gain of 2.

Biasing the external amplifier with an offset from the reference

voltage, results in full 4-quadrant multiplying operation. The

transfer function of this circuit shows that both negative and

positive output voltages are created as the input data (D) is

incremented from code zero (VOUT = –VREF) to midscale (VOUT =

0 V) to full scale (VOUT = +VREF).

()

REF

OUT

−

−1

where D is the fractional representation of the digital word

loaded to the DAC and n is the resolution of the DAC.

D = 0 to 255 (8-bit AD5424)

= 0 to 1023 (10-bit AD5433)

= 0 to 4095 (12-bit AD5445)

When VIN is an ac signal, the circuit performs 4-quadrant

multiplication.

Table 8 shows the relationship between digital code and the

expected output voltage for bipolar operation (AD5424,

8-bit device).

Table 8. Bipolar Code Table

Digital Input

Analog Output (V)

1111 1111

+VREF (127/128)

1000 0000

0000 0001

–VREF (127/128)

0000 0000

–VREF (128/128)

Stability

In the I-to-V configuration, the IOUT of the DAC and the

inverting node of the op amp must be connected as closely as

possible and proper PCB layout techniques must be employed.

Since every code change corresponds to a step function, gain

peaking may occur if the op amp has limited GBP and there is

excessive parasitic capacitance at the inverting node. This

parasitic capacitance introduces a pole into the open-loop

response, which can cause ringing or instability in closed-

loop applications.

An optional compensation capacitor, C1, can be added in

parallel with RFB for stability, as shown in Figure 49 and

Figure 50. Too small a value of C1 can produce ringing at the

output, while too large a value can adversely affect the settling

time. C1 should be found empirically, but 1 pF to 2 pF is

generally adequate for compensation.

AD5433 Datasheet(PDF) 18 Page - Analog Devices

AD5433 Datasheet(HTML) 18 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Datasheet Download

Link URL