AD9650 datasheet(35/44 Pages) AD

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AD9650

Rev. 0 | Page 35 of 44

determined by the sample rate and the characteristics of the

analog input signal.

Reducing the capacitive load presented to the output drivers

reduces digital power consumption.

By asserting PDWN (either through the SPI port or by asserting

the PDWN pin high), the AD9650 is placed in power-down

mode. In this state, the ADC typically dissipates 3.3 mW.

During power-down, the output drivers are placed in a high

impedance state. Asserting the PDWN pin low returns the

AD9650 to its normal operating mode.

Low power dissipation in power-down mode is achieved by

shutting down the reference, reference buffer, biasing networks,

and clock. Internal capacitors are discharged when entering power-

down mode and must be recharged when returning to normal

operation.

When using the SPI port interface, the user can place the ADC

in power-down mode or standby mode. Standby mode allows

the user to keep the internal reference circuitry powered when

faster wake-up times are required.

DIGITAL OUTPUTS

The AD9650 output drivers can be configured to interface with

1.8 V CMOS logic families. The AD9650 can also be configured

for LVDS outputs (standard ANSI or reduced output swing mode)

using a DRVDD supply voltage of 1.8 V.

In CMOS output mode, the output drivers are sized to provide

sufficient output current to drive a wide variety of logic families.

However, large drive currents tend to cause current glitches on

the supplies that may affect converter performance.

Applications requiring the ADC to drive large capacitive loads

or large fanouts may require external buffers or latches.

The default output mode is CMOS, with each channel output

on a separate bus, as shown in Figure 2. The output can also be

configured for interleaved CMOS via the SPI port. In interleaved

CMOS mode, the data for both channels is output through the

Channel A output pins, and the Channel B output is placed into

high impedance mode. The timing diagram for interleaved

CMOS output mode is shown in Figure 3.

The output data format can be selected for either offset binary

or twos complement by setting the SCLK/DFS pin when operating

in the external pin mode (see Table 12).

As detailed in the AN-877 Application Note, Interfacing to High

Speed ADCs via SPI, the data format can be selected for offset

binary, twos complement, or gray code when using the SPI control.

Table 12. SCLK/DFS Mode Selection (External Pin Mode)

Voltage at Pin

SCLK/DFS

SDIO/DCS

AGND

Offset binary (default)

DCS disabled

AVDD

Twos complement

DCS enabled

(default)

Digital Output Enable Function (OEB)

The AD9650 has a flexible three-state ability for the digital output

pins. The three-state mode is enabled using the OEB pin or

through the SPI. If the OEB pin is low, the output data drivers and

DCOs are enabled. If the OEB pin is high, the output data drivers

and DCOs are placed in a high impedance state. This OEB

function is not intended for rapid access to the data bus. Note

that OEB is referenced to the digital output driver supply

(DRVDD) and should not exceed that supply voltage.

When using the SPI, the data outputs and DCO of each channel

can be independently three-stated by using the output enable

bar bit (Bit 4) in Register 0x14.

TIMING

The AD9650 provides latched data with a pipeline delay of

12 clock cycles. Data outputs are available one propagation

delay (tPD) after the rising edge of the clock signal.

The length of the output data lines and loads placed on them

should be minimized to reduce transients within the AD9650.

These transients can degrade converter dynamic performance.

The lowest typical conversion rate of the AD9650 is 10 MSPS.

At clock rates below 10 MSPS, dynamic performance can

degrade.

Data Clock Output (DCO)

The AD9650 provides two data clock output (DCO) signals

intended for capturing the data in an external register. In CMOS

output mode, the data outputs are valid on the rising edge of DCO,

unless the DCO clock polarity has been changed via the SPI. In

LVDS output mode, the DCO and data output switching edges

are closely aligned. Additional delay can be added to the DCO

output using SPI Register 0x17 to increase the data setup time.

In this case, the Channel A output data is valid on the rising

edge of DCO, and the Channel B output data is valid on the

falling edge of DCO. See Figure 2, Figure 3, and Figure 4 for a

graphical timing description of the output modes.

Table 13. Output Data Format

Input (V)

Condition (V)

Offset Binary Output Mode

Twos Complement Mode

ORx

VIN+ − VIN−

< −VREF − 0.5 LSB

0000 0000 0000 0000

1000 0000 0000 0000

VIN+ − VIN−

= −VREF

0000 0000 0000 0000

1000 0000 0000 0000

VIN+ − VIN−

= 0 V

1000 0000 0000 0000

0000 0000 0000 0000

VIN+ − VIN−

= +VREF − 1.0 LSB

1111 1111 1111 1111

0111 1111 1111 1111

VIN+ − VIN−

> +VREF − 0.5 LSB

1111 1111 1111 1111

0111 1111 1111 1111

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