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AD9650 Datasheet(PDF) 33 Page - Analog Devices |
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AD9650 Datasheet(HTML) 33 Page - Analog Devices |
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33 / 44 page  AD9650 Rev. 0 | Page 33 of 44 Clock Input Considerations For optimum performance, the AD9650 sample clock inputs, CLK+ and CLK−, should be clocked with a differential signal. The signal is typically ac-coupled into the CLK+ and CLK− pins via a transformer or capacitors. These pins are biased internally (see Figure 86) and require no external bias. If the inputs are floated, the CLK− pin is pulled low to prevent spurious clocking. AVDD CLK+ 9pF 9pF CLK– 0.9V Figure 86. Equivalent Clock Input Circuit Clock Input Options The AD9650 has a very flexible clock input structure. Clock input can be a CMOS, LVDS, LVPECL, or sine wave signal. Regardless of the type of signal being used, clock source jitter is of the most concern, as described in the Jitter Considerations section. Figure 87 and Figure 88 show two preferred methods for clocking the AD9650 (at clock rates up to 625 MHz). A low jitter clock source is converted from a single-ended signal to a differential signal using either an RF balun or an RF transformer. The RF balun configuration is recommended for clock frequencies between 125 MHz and 625 MHz, and the RF transformer is recom- mended for clock frequencies from 10 MHz to 200 MHz. The back-to-back Schottky diodes across the transformer/balun’s secondary windings limit the clock excursions into the AD9650 to approximately 0.8 V p-p differential. This limit helps prevent the large voltage swings of the clock from feeding through to other portions of the AD9650 while preserving the fast rise and fall times of the signal that are critical to a low jitter performance. 0.1µF 0.1µF 0.1µF 0.1µF SCHOTTKY DIODES: HSMS2822 CLOCK INPUT 50Ω 100Ω CLK– CLK+ ADC AD9650 Mini-Circuits® ADT1-1WT, 1:1Z XFMR Figure 87. Transformer-Coupled Differential Clock (Up to 200 MHz) 0.1µF 0.1µF 1nF CLOCK INPUT 1nF 50Ω CLK– CLK+ SCHOTTKY DIODES: HSMS2822 ADC AD9650 Figure 88. Balun-Coupled Differential Clock (Up to 625 MHz) If a low jitter clock source is not available, another option is to ac couple a differential PECL signal to the sample clock input pins, as shown in Figure 89. The AD9510/AD9511/AD9512/ AD9513/AD9514/AD9515/AD9516/AD9517/AD9518 clock drivers offer excellent jitter performance. 0.1µF 0.1µF 0.1µF 0.1µF 240Ω 240Ω 100Ω PECL DRIVER 50kΩ 50kΩ CLK– CLK+ CLOCK INPUT CLOCK INPUT AD951x ADC AD9650 Figure 89. Differential PECL Sample Clock (Up to 625 MHz) A third option is to ac couple a differential LVDS signal to the sample clock input pins, as shown in Figure 90. The AD9510/ AD9511/AD9512/AD9513/AD9514/AD9515/AD9516/AD9517/ AD9518 clock drivers offer excellent jitter performance. 100Ω 0.1µF 0.1µF 0.1µF 0.1µF 50kΩ 50kΩ CLK– CLK+ CLOCK INPUT CLOCK INPUT AD951x LVDS DRIVER ADC AD9650 Figure 90. Differential LVDS Sample Clock (Up to 625 MHz) In some applications, it may be acceptable to drive the sample clock inputs with a single-ended CMOS signal. In such applica- tions, the CLK+ pin should be driven directly from a CMOS gate, and the CLK− pin should be bypassed to ground with a 0.1 μF capacitor (see Figure 91). OPTIONAL 100Ω 0.1µF 0.1µF 0.1µF 50Ω1 150Ω RESISTOR IS OPTIONAL. CLK– CLK+ VCC 1kΩ 1kΩ CLOCK INPUT AD951x CMOS DRIVER ADC AD9650 Figure 91. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz) Input Clock Divider The AD9650 contains an input clock divider with the ability to divide the input clock by integer values between 1 and 8. For divide ratios of 1, 2, 4, or 8, the duty cycle stabilizer (DCS) is optional. For other divide ratios, divide-by-3, -5, -6, and -7, the duty cycle stabilizer must be enabled for proper part operation. The AD9650 clock divider can be synchronized using the external SYNC input. Bit 0 to Bit 2 of Register 0x100 allow the clock divider to be resynchronized on every SYNC signal or only on the first SYNC signal after the register is written. A valid SYNC causes the clock divider to reset to its initial state. This synchro- nization feature allows multiple parts to have their clock dividers aligned to guarantee simultaneous input sampling. |
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