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AD9650

Rev. 0 | Page 34 of 44

Clock Duty Cycle

Typical high speed ADCs use both clock edges to generate a variety

of internal timing signals and, as a result, may be sensitive to clock

duty cycle. The AD9650 requires a tight tolerance on the clock duty

cycle to maintain dynamic performance characteristics.

The AD9650 contains a duty cycle stabilizer (DCS) that retimes

the nonsampling (falling) edge, providing an internal clock signal

with a nominal 50% duty cycle. This allows the user to provide

a wide range of clock input duty cycles without affecting the

performance of the AD9650. Noise and distortion performance

are nearly flat for a wide range of duty cycles with the DCS

enabled.

Jitter in the rising edge of the input is still of paramount concern

and is not easily reduced by the internal stabilization circuit. The

duty cycle control loop does not function for clock rates of less

than 20 MHz, nominally. The loop has a time constant associated

with it that must be considered in applications in which the clock

rate can change dynamically. A wait time of 1.5 μs to 5 μs is

required after a dynamic clock frequency increase or decrease

before the DCS loop is relocked to the input signal. During the

time period that the loop is not locked, the DCS loop is bypassed,

and internal device timing is dependent on the duty cycle of the

input clock signal. In such applications, it may be appropriate to

disable the duty cycle stabilizer. In all other applications, enabling

the DCS circuit is recommended to maximize ac performance.

Jitter Considerations

High speed, high resolution ADCs are sensitive to the quality

of the clock input. For inputs near full scale, the degradation in

SNR from the low frequency SNR (SNRLF) at a given input

frequency (fINPUT) due to jitter (tJRMS) can be calculated by

SNRHF = −10 log[(2π × fINPUT × tJRMS)2 + 10

]

)

(

SNR

−

In the equation, the rms aperture jitter represents the clock input

jitter specification.

Improvements in SNR can be achieved for IF undersampling

applications by minimizing the effects of aperture jitter. This

can be accomplished by applying a high frequency clock input

and using the integrated clock divider to achieve the desired

sample rate of the ADC core. Inherently, the jitter performance

of the AD9650 improves as the frequency of the clock increases.

This is a result of the slew rate of the clock affecting the noise

performance of the ADC, where fast transition edges result in

the best performance. Figure 92 shows the improvement in SNR

for the different clock divide ratios for the 1 V p-p and 2 V p-p

sinusoidal clock inputs. Measurements in Figure 92 were taken

for the AD9650BCPZ-105 where the input frequency was

141 MHz. The same analysis can be performed for the various

speed grades of the AD9650 family of parts.

CLK DIVIDE RATIO

1V p-p CLK AMPLITUDE

2V p-p CLK AMPLITUDE

Figure 92. SNR vs. CLK Divide Ratio for fIN = 141 MHz and a

Sample Rate of 105 MSPS

The clock input should be treated as an analog signal in cases in

which aperture jitter may affect the dynamic range of the AD9650.

Power supplies for clock drivers should be separated from the

ADC output driver supplies to avoid modulating the clock signal

with digital noise. Low jitter, crystal-controlled oscillators make

the best clock sources.

Refer to the AN-501 Application Note and the AN-756 Application

Note (visit www.analog.com) for more information about jitter

performance as it relates to ADCs.

CHANNEL/CHIP SYNCHRONIZATION

The AD9650 has a SYNC input that offers the user flexible

synchronization options for synchronizing the clock divider.

The clock divider sync feature is useful for guaranteeing synchro-

nized sample clocks across multiple ADCs. The input clock

divider can be enabled to synchronize on a single occurrence of

the SYNC signal or on every occurrence.

The SYNC input is internally synchronized to the sample clock;

however, to ensure that there is no timing uncertainty between

multiple parts, the SYNC input signal should be externally syn-

chronized to the input clock signal, meeting the setup and hold

times shown in Table 5. The SYNC input should be driven using

a single-ended CMOS-type signal.

POWER DISSIPATION AND STANDBY MODE

The power dissipated by the AD9650 varies with its sample rate.

In CMOS output mode, the digital power dissipation is determined

primarily by the strength of the digital drivers and the load on

each output bit.

The maximum DRVDD current (IDRVDD) can be calculated as

IDRVDD = VDRVDD × CLOAD × fCLK × N

where N is the number of output bits (32 plus two DCO outputs

in the case of the AD9650).

This maximum current occurs when every output bit switches on

every clock cycle, that is, a full-scale square wave at the Nyquist

frequency of fCLK/2. In practice, the DRVDD current is estab-

lished by the average number of output bits switching, which is

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