TDA18211HD datasheet(17/66 Pages) NXP

17 / 66 page

TDA18211HD_5

Product data sheet

Rev. 05 — 2 June 2009

17 of 66

NXP Semiconductors

TDA18211HD

DVB-T Silicon Tuner IC

The image rejection calibration consists in optimizing some tunable parameters inside the

mixer throughout a set of internal measurements, leading to ensure a 65 dB typical value

of image rejection. The internal signal used during this phase is generated by the PLL

calibration (CAL PLL).

The RF tracking ﬁlters central frequency can be adjusted with the tuning word

RFC_CPROG. The RF tracking ﬁlters calibration (RFCAL) consists of an internal tone at

the input of the tracking ﬁlters (with the CAL PLL), and ﬁnding the RFC_CPROG

corresponding to the maximum transmitted power. The RFCAL is just a little part of a

more complex algorithm fully described in the ﬂowcharts in Section 9.4.

The Power detection mode is a Normal mode where the detector used for the calibrations

is switched ON. This special mode enables to sense the power at the input of the

TDA18211HD and makes the power scan algorithm possible (see Section 9.4.8

“Flowchart TDA18211PowerScan”).

9.3.9 Description of Easy Prog byte 5

9.3.10 Description of Cal Post-Divider byte

9.3.11 Description of Cal divider bytes 1, 2 and 3

Table 18.

EP5 - Easy Prog byte 5 (subaddress 07h) bit description

Legend: * power-on reset value

Bit

Symbol

Access

Value

Description

EXTENDED_REG

R/W

enables the extended register addressing

extended register (00h to 26h)

limited register (00h to 0Fh); only 1 byte can

be programmed after address 0Fh within 1

transmission

6 to 4 IR_GSTEP[2:0]

R/W

011*

gain step for image rejection calibration

R/W

must be set to logic 0

2 to 0 IR_MEAS[2:0]

R/W

000*

image rejection measurement frequency range

(see Table 51)

Table 19.

CPD - Cal Post-Divider byte (subaddress 08h) bit description

Legend: * power-on reset value

Bit

Symbol

Access

Value

Description

7 to 0

CAL_POST_DIV[7:0]

R/W

00h*

calibration synthesizer post-divider (see

Table 46)

Table 20.

CD1, CD2 and CD3 - Cal divider bytes 1, 2 and 3 (address 09h, 0Ah and 0Bh) bit

description

Legend: * power-on reset value

Address

Bit

Symbol

Access

Value Description

09h

CD1

R/W

must be set to logic 0

6 to 0 CAL_DIV[22:16]

R/W

00h*

calibration synthesizer main

divider bits

0Ah

CD2

7 to 0 CAL_DIV[15:8]

R/W

00h*

0Bh

CD3

7 to 0 CAL_DIV[7:0]

R/W

00h*

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