82801BA datasheet(7/498 Pages) INTEL

7 / 498 page

82801BA ICH2 and 82801BAM ICH2-M

Datasheet

vii

Functional Description ...............................................................................................5-1

5.1

Hub Interface to PCI Bridge (D30:F0)...........................................................5-1

5.1.1

PCI Bus Interface.............................................................................5-1

5.1.2

PCI-to-PCI Bridge Model .................................................................5-2

5.1.3

IDSEL to Device Number Mapping ..................................................5-2

5.1.4

SERR# Functionality........................................................................5-2

5.1.5

Parity Error Detection.......................................................................5-4

5.1.6

Standard PCI Bus Configuration Mechanism ..................................5-5

5.1.7

PCI Dual Address Cycle (DAC) Support

(82801BA ICH2 only) .......................................................................5-6

5.2

LAN Controller (B1:D8:F0)............................................................................5-6

5.2.1

LAN Controller Architectural Overview ............................................5-7

5.2.2

LAN Controller PCI Bus Interface ....................................................5-9

5.2.2.1

Bus Slave Operation.........................................................5-9

5.2.2.2

Bus Master Operation.....................................................5-10

5.2.3

CLOCKRUN# Signal (82801BAM ICH2-M only)............................5-13

5.2.3.1

PCI Power Management ................................................5-13

5.2.3.2

PCI Reset Signal ............................................................5-15

5.2.3.3

Wake-up Events .............................................................5-15

5.2.3.4

Wake on LAN (Preboot Wake-up) ..................................5-16

5.2.4

Serial EEPROM Interface ..............................................................5-17

5.2.5

CSMA/CD Unit ...............................................................................5-19

5.2.6

Media Management Interface ........................................................5-20

5.2.7

TCO Functionality ..........................................................................5-20

5.3

LPC Bridge (w/ System and Management Functions) (D31:F0).................5-20

5.3.1

LPC Interface .................................................................................5-21

5.3.1.1

LPC Cycle Types............................................................5-21

5.3.1.2

Start Field Definition .......................................................5-22

5.3.1.3

Cycle Type / Direction (CYCTYPE + DIR)......................5-22

5.3.1.4

Size.................................................................................5-22

5.3.1.5

SYNC..............................................................................5-23

5.3.1.6

SYNC Time-out ..............................................................5-23

5.3.1.7

SYNC Error Indication ....................................................5-23

5.3.1.8

LFRAME# Usage............................................................5-24

5.3.1.9

I/O Cycles .......................................................................5-25

5.3.1.10 Bus Master Cycles..........................................................5-25

5.3.1.11 LPC Power Management ...............................................5-25

5.3.1.12 Configuration and ICH2 Implications ..............................5-25

5.4

DMA Operation (D31:F0) ............................................................................5-26

5.4.1

Channel Priority .............................................................................5-26

5.4.2

Address Compatibility Mode ..........................................................5-27

5.4.3

Summary of DMA Transfer Sizes ..................................................5-27

5.4.4

Autoinitialize ...................................................................................5-28

5.4.5

Software Commands .....................................................................5-29

5.5

PCI DMA .....................................................................................................5-30

5.5.1

PCI DMA Expansion Protocol ........................................................5-30

5.5.2

PCI DMA Expansion Cycles ..........................................................5-32

5.5.3

DMA Addresses .............................................................................5-32

5.5.4

DMA Data Generation....................................................................5-32

5.5.5

DMA Byte Enable Generation ........................................................5-33

5.5.6

DMA Cycle Termination .................................................................5-33

5.5.7

LPC DMA .......................................................................................5-33

82801BA Datasheet(PDF) 7 Page - Intel Corporation

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