82801BA datasheet(32/498 Pages) INTEL

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Introduction

1-4

82801BA ICH2 and 82801BAM ICH2-M Datasheet

The following sub-sections provide an overview of the ICH2 capabilities.

Hub Architecture

As I/O speeds increase, the demand placed on the PCI bus by the I/O bridge has become

significant. With the addition of AC’97 and Ultra ATA/100, coupled with the existing USB, I/O

requirements could impact PCI bus performance. The chipset’s hub interface architecture ensures

that the I/O subsystem; both PCI and the integrated I/O features (IDE, AC’97, USB, etc.), will

receive adequate bandwidth. By placing the I/O bridge on the hub interface (instead of PCI), the

hub architecture ensures that both the I/O functions integrated into the ICH2 and the PCI

peripherals obtain the bandwidth necessary for peak performance.

PCI Interface

The ICH2 PCI interface provides a 33 MHz, Rev. 2.2 compliant implementation. All PCI signals

are 5V tolerant, except PME#. The ICH2 integrates a PCI arbiter that supports up to six external

PCI bus masters in addition to the internal ICH2 requests.

IDE Interface (Bus Master capability and synchronous DMA Mode)

The fast IDE interface supports up to four IDE devices providing an interface for IDE hard disks

and CD ROMs. Each IDE device can have independent timings. The IDE interface supports PIO

IDE transfers up to 14 Mbytes/sec and Bus Master IDE transfers up 100 Mbytes/sec. It does not

consume any ISA DMA resources. The IDE interface integrates 16x32-bit buffers for optimal

transfers.

The ICH2’s IDE system contains two independent IDE signal channels. They can be electrically

isolated independently. They can be configured to the standard primary and secondary channels

(four devices). There are integrated series resistors on the data and control lines (see Section 5.15,

“IDE Controller (D31:F1)” on page 5-99 for details).

Low Pin Count (LPC) Interface

The ICH2 implements an LPC Interface as described in the LPC 1.0 specification. The Low Pin

Count (LPC) Bridge function of the ICH2 resides in PCI Device 31:Function 0. In addition to the

LPC bridge interface function, D31:F0 contains other functional units including DMA, Interrupt

Controllers, Timers, Power Management, System Management, GPIO, and RTC.

Note that in the current chipset platform, the Super I/O (SIO) component has migrated to the Low

Pin Count (LPC) interface. Migration to the LPC interface allows for lower cost Super I/O designs.

82801BA Datasheet(PDF) 32 Page - Intel Corporation