82801BA datasheet(46/498 Pages) INTEL

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Signal Description

2-10

82801BA ICH2 and 82801BAM ICH2-M Datasheet

2.12

SMBus Interface

2.13

System Management Interface

RCIN#

Keyboard Controller Reset Processor: The keyboard controller can generate

INIT# to the processor. This saves the external OR gate with the ICH2’s other

sources of INIT#. When the ICH2 detects the assertion of this signal, INIT# is

generated for 16 PCI clocks.

A20GATE

A20 Gate: This signal is from the keyboard controller. It acts as an alternative

method to force the A20M# signal active. A20GATE saves the external OR gate

needed with various other PCIsets.

CPUPWRGD

Processor Power Good (82801BA ICH2): This signal should be connected to

the processor’s PWRGOOD input. This is an open-drain output signal (external

pull-up resistor required) that represents a logical AND of the ICH2’s PWROK and

VRMPWRGD signals.

CPU Power Good (82801BAM ICH2-M): This signal should be connected to the

processor’s PWRGOOD input. For Intel® SpeedStep™ technology support, this

signal is kept high during a Intel® SpeedStep™ technology state transition to

prevent loss of processor context. This is an open-drain output signal (external

pull-up resistor required) that represents a logical AND of the ICH2-M’s PWROK

and VGATE / VRMPWRGD signals.

Table 2-12. SM Bus Interface Signals

Name

Type

Description

SMBDATA

I/OD

SMBus Data: External pull-up is required.

SMBCLK

I/OD

SMBus Clock: External pull-up is required.

SMBALERT#/

GPIO[11]

SMBus Alert: This signal is used to wake the system or generate an SMI#. If not

used for SMBALERT#, it can be used as a GPI.

Table 2-13. System Management Interface Signals

Name

Type

Description

INTRUDER#

Intruder Detect: This signal can be set to disable system if box detected open.

This signal’s status is readable, so it can be used like a GPI if the Intruder

Detection is not needed.

SMLINK[1:0]

I/OD

System Management Link: These signals are an SMBus link to an optional

external system management ASIC or LAN controller. External pull-ups are

required.

Note that SMLINK[0] corresponds to an SMBus Clock signal and SMLINK[1]

corresponds to an SMBus Data signal.

Table 2-11. Processor Interface Signals (Continued)

Name

Type

Description

Note

82801BA ICH2: The 82801BA ignores RCIN# assertion during transitions to the

S3, S4 and S5 states.

82801BAM ICH2-M: The 82801BAM ignores RCIN# assertion during transitions

to the S1, S3, S4 and S5 states.

82801BA Datasheet(PDF) 46 Page - Intel Corporation

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