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82801BA ICH2 and 82801BAM ICH2-M Datasheet

2-7

Signal Description

2.9

USB Interface

2.10

Power Management Interface

Table 2-9. USB Interface Signals

Name

Type

Description

USBP0P,

USBP0N,

USBP1P,

USBP1N

I/O

Universal Serial Bus Port 1:0 Differential: These differential pairs are used to

transmit Data/Address/Command signals for ports 0 and 1 (USB Controller 1).

USBP2P,

USBP2N,

USBP3P,

USBP3N

I/O

Universal Serial Bus Port 3:2 Differential: These differential pairs are used to

transmit Data/Address/Command signals for ports 2 and 3

(USB Controller 2).

OC[3:0]#

Overcurrent Indicators: These signals set corresponding bits in the USB

controllers to indicate that an overcurrent condition has occurred.

Table 2-10. Power Management Interface Signals

Name

Type

Description

THRM#

Thermal Alarm: THRM# is an active low signal generated by external hardware to

start the hardware clock throttling mode. This signal can also generate an SMI# or

an SCI.

SLP_S1#

(ICH2-M only)

S1 Sleep Control: Clock synthesizer or power plane control. This signal connects

to clock synthesizer’s PWRDWN# signal. An optional use is to shut off power to

non-critical systems when in the S1 (Powered On Suspend), S3 (Suspend To

RAM), S4 (Suspend to Disk), or S5 (Soft Off) states.

SLP_S3#

S3 Sleep Control: Power plane control. This signal is used to shut off power to all

non-critical systems when in S3 (Suspend To RAM), S4 (Suspend to Disk) or S5

(Soft Off) states.

SLP_S5#

S5 Sleep Control: Power plane control. This signal is used to shut power off to all

non-critical systems when in the S4 (Suspend To Disk) or S5 (Soft Off) states.

PWROK

Power OK: When asserted, PWROK is an indication to the ICH2 that core power

and PCICLK have been stable for at least 1 ms. PWROK can be driven

asynchronously. When PWROK is negated, the ICH2 asserts PCIRST#.

RSM_PWROK

(ICH2 0nly)

Resume Well Power OK: When asserted, this signal is an indication to the ICH2

that the resume well power (VccSus3_3, VccSus1_8) has been stable for at least

10 ms.

LAN_PWROK

(ICH2-M only)

LAN Power OK: When asserted, this signal is an indication to the ICH2-M that the

LAN Controller power (VccLAN3_3, VccLAN1_8) has been stable for at least

10 ms.

PWRBTN#

Power Button: The Power Button will cause SMI# or SCI to indicate a system

request to go to a sleep state. If the system is already in a sleep state, this signal

will cause a wake event. If PWRBTN# is pressed for more than 4 seconds, this will

cause an unconditional transition (power button override) to the S5 state with only

the PWRBTN# available as a wake event. Override will occur even if the system is

in the S1-S4 states. This signal has an internal pull-up resistor.

RI#

Ring Indicate: From the modem interface. This signal can be enabled as a wake

event; this is preserved across power failures.

RSMRST#

Resume Well Reset: RSMRST# is used for resetting the resume power plane

logic.

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