82801BA datasheet(3/498 Pages) INTEL

3 / 498 page

82801BA ICH2 and 82801BAM ICH2-M

Datasheet

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Intel® 82801BA/M ICH2/ICH2-M Features

I PCI Bus I/F

— Supports PCI at 33 MHz

— Supports PCI Rev 2.2 Specification

— 133 MByte/sec maximum throughput

— Supports up to 6 master devices on PCI

— One PCI REQ/GNT pair can be given higher

arbitration priority (intended for external

1394 host controller)

I Integrated LAN Controller

— WfM 2.0 Compliant

— Interface to discrete LAN Connect

component

— 10/100 Mbit/sec Ethernet support

— 1 Mbit/sec HomePNA* support

I Integrated IDE Controller

— Independent timing of up to 4 drives

— Ultra ATA/100/66/33, BMIDE and PIO

modes

— Read transfers up to 100MB/s, Writes to

89 MB/s

— Separate IDE connections for Primary and

Secondary cables

— Implements Write Ping-Pong Buffer for

faster write performance

I USB

— 2 UHCI Host Controllers with a total of

4 ports

—USB 1.1 compliant

— Supports wake-up from sleeping states

S1–S4

— Supports legacy Keyboard/Mouse software

I AC'97 Link for Audio and Telephony CODECs

— AC’97 2.1 compliant

— Independent bus master logic for 5 channels

(PCM In/Out, Mic Input, Modem In/Out)

— Separate independent PCI functions for

Audio and Modem

— Support for up to six channels of PCM audio

output (full AC3 decode)

— Supports wake-up events

I Interrupt Controller

— Support up to 8 PCI interrupt pins

— Supports PCI 2.2 Message-Based Interrupts

— Two cascaded 82C59

— Integrated I/O APIC capability

— 15 interrupts supported in 8259 mode, 24

supported in I/O APIC mode

— Supports Serial Interrupt Protocol

— Supports Front-Side Bus interrupt delivery

I 1.8 V operation with 3.3 V I/O

— 5V tolerant buffers on IDE, PCI, USB Over-

current and Legacy signals

I GPIO

— TTL, Open-Drain, Inversion

I Timers Based on 82C54

— System timer, Refresh request, Speaker tone

output

I Power Management Logic

— ACPI 1.0 compliant

— ACPI Power Management Timer

— PCI PME# support

— SMI# generation

— All registers readable/restorable for proper

resume from 0V suspend states

— Support for APM-based legacy power

management for non-ACPI implementations

I External Glue Integration

— Integrated Pull-up, Pull-down and Series

Termination resistors on IDE and processor

interface

I Enhanced Hub I/F buffers improve routing

flexibility (Not available with all Memory

Controller Hubs)

I Firmware Hub (FWH) I/F supports BIOS

memory size up to 8 MBs

I Low Pin count (LPC) I/F

— Allows connection of legacy ISA and X-Bus

devices such as Super I/O

— Supports two Master/DMA devices.

I Enhanced DMA Controller

— Two cascaded 8237 DMA controllers

— PCI DMA: Supports PC/PCI — Includes

two PC/PCI REQ#/GNT# pairs

— Supports LPC DMA

— Supports DMA Collection Buffer to provide

Type-F DMA performance for all DMA

channels

I Real-Time Clock

— 256-byte battery-backed CMOS RAM

— Hardware implementation to indicate century

rollover

I System TCO Reduction Circuits

— Timers to generate SMI# and Reset upon

detection of system hang

— Timers to detect improper processor reset

— Integrated processor frequency strap logic

I SM Bus

— Host interface allows processor to

communicate via SM Bus

— Slave interface allows an external

Microcontroller to access system resources

— Compatible with most 2-Wire components

that are also I2C compatible

I Supports ISA bus via external PCI-ISA Bridge

I 360-pin EBGA package

— Tri-state modes to enable mobile swap bay

(82801BAM ICH2-M)

— ACPI-defined power states

- C1–C2, S3–S5 (82801BA ICH2)

- C1–C3, S1, S3–S5 (82801BAM ICH2-M)

— Support for “Intel® SpeedStep™

technology” processor power control

(82801BAM ICH2-M)

— PCI CLKRUN# support

(82801BAM ICH2-M)

The Intel® 82801BA ICH2 and 82801BAM ICH2-M may contain design defects or errors known as errata which may cause the

products to deviate from published specifications. Current characterized errata are available on request.

Shading,as is shown here, indicates differences between the two components.

82801BA Datasheet(PDF) 3 Page - Intel Corporation

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