82801BA datasheet(83/498 Pages) INTEL

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82801BA ICH2 and 82801BAM ICH2-M Datasheet

5-21

Functional Description

5.3.1

LPC Interface

The ICH2 implements an LPC interface as described in the LPC 1.0 specification. The LPC

interface to the ICH2 is shown in Figure 5-6. Note that the ICH2 implements all of the signals that

are shown as optional, but peripherals are not required to do so.

5.3.1.1

LPC Cycle Types

The ICH2 implements all of the cycle types described in the LPC I/F 1.0 specification. Table 5-3

shows the cycle types supported by the ICH2.

NOTES:

1. For memory cycles below 16 MB which do not target enabled FWH ranges, the ICH2will perform standard

LPC memory cycles. It will only attempt 8-bit transfers. If the cycle appears on PCI as a 16-bit transfer, it will

appear as two consecutive 8-bit transfers on LPC. Likewise, if the cycle appears as a 32-bit transfer on PCI,

it will appear as four consecutive 8-bit transfers on LPC. If the cycle is not claimed by any peripheral, it will be

subsequently aborted, and the ICH2 will return a value of all 1s to the processor. This is done to maintain

compatibility with ISA memory cycles where pull-up resistors would keep the bus high if no device responds.

2. Bus Master Read or Write cycles must be naturally aligned. For example, a 1-byte transfer can be to any

address. However, the 2-byte transfer must be word aligned (i.e. with an address where A0=0). A DWord

transfer must be DWord aligned (i.e., with an address where A1and A0 are both 0)

Figure 5-6. LPC Interface Diagram

ICH

Super I/O

PCI Bus

PCI

CLK

PCI

RST#

LAD[3:0]

PCI

SERIRQ

LPCPD#

(optional)

PCI

PME#

LSMI#

(optional)

LFRAME#

LDRQ#

(optional)

GPI

SUS_STAT#

ICH2

Table 5-3. LPC Cycle Types Supported

Cycle Type

Comment

Memory Read

Single: 1 byte only

Memory Write

Single: 1 byte only

I/O Read

1 byte only. ICH2 breaks up 16 and 32-bit processor cycles into multiple 8-bit

transfers. See Note 1 below.

I/O Write

1 byte only. ICH2 breaks up 16 and 32-bit processor cycles into multiple 8-bit

transfers. See Note 1 below.

DMA Read

Can be 1 or 2 bytes

DMA Write

Can be 1 or 2 bytes

Bus Master Read

Can be 1, 2, or 4 bytes. (See Note 2 below)

Bus Master Write

Can be 1, 2, or 4 bytes. (See Note 2 below)

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