82801BA datasheet(71/498 Pages) INTEL

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82801BA ICH2 and 82801BAM ICH2-M Datasheet

5-9

Functional Description

5.2.2

LAN Controller PCI Bus Interface

As a Fast Ethernet Controller, the role of the ICH2 integrated LAN Controller is to access

transmitted data or deposit received data. The LAN Controller, as a bus master device, initiates

memory cycles via the PCI bus to fetch or deposit the required data.

To perform these actions, the LAN Controller is controlled and examined by the processor via its

control and status structures and registers. Some of these control and status structures reside in the

LAN Controller and some reside in system memory. For access to the LAN Controller’s Control/

Status Registers (CSR), the LAN Controller acts as a slave (in other words, a target device). The

LAN Controller serves as a slave also while the processor accesses the EEPROM.

5.2.2.1

Bus Slave Operation

The ICH2 integrated LAN Controller serves as a target device in one of the following cases:

• Processor accesses to the LAN Controller System Control Block (SCB) Control/Status

Registers (CSR)

• Processor accesses to the EEPROM through its CSR

• Processor accesses to the LAN Controller PORT address via the CSR

• Processor accesses to the MDI control register in the CSR

• PCI Configuration cycles

The size of the CSR memory space is 4 KB in the memory space and 64 bytes in the I/O space. The

LAN Controller treats accesses to these memory spaces differently.

Control/Status Register (CSR) Accesses

The integrated LAN Controller supports zero wait state single cycle memory or I/O mapped

accesses to its CSR space. Separate BARs request 4 KB of memory space and 64 bytes of I/O

space to accomplish this. Based on its needs, the software driver uses either memory or I/O

mapping to access these registers. The LAN Controller provides 4 KB of CSR space, which

includes the following elements:

• System Control Block (SCB) registers

• PORT register

• EEPROM control register

• MDI control register

• Flow control registers

In the case of accessing the Control/Status Registers, the processor is the initiator and the LAN

Controller is the target.

Read Accesses: The processor, as the initiator, drives address lines AD[31:0], the command and

byte enable lines C/BE[3:0]#, and the control lines IRDY# and FRAME#. As a slave, the LAN

Controller controls the TRDY# signal and provides valid data on each data access. The LAN

Controller allows the processor to issue only one read cycle when it accesses the Control/Status

Registers, generating a disconnect by asserting the STOP# signal. The processor can insert wait

states by deasserting IRDY# when it is not ready.

82801BA Datasheet(PDF) 71 Page - Intel Corporation

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