82801BA datasheet(75/498 Pages) INTEL

75 / 498 page

82801BA ICH2 and 82801BAM ICH2-M Datasheet

5-13

Functional Description

Note:

This feature is not recommended for use in non-cache line oriented systems since it may cause

shorter bursts and lower performance.

Note:

This feature should be used only when the CLS register in PCI Configuration space is set to 8 or

16.

Note:

The LAN Controller reads all control data structures (including Receive Buffer Descriptors) from

the first DWord (even if it is not required) to maintain cache line alignment.

Error Handling

Data Parity Errors: As an initiator, the LAN Controller checks and detects data parity errors that

occur during a transaction. If the Parity Error Response bit is set (PCI Configuration Command

Configuration Status register, bit 8). In addition, if the error was detected by the LAN Controller

during read cycles, it sets the Detected Parity Error bit (PCI Configuration Status register, bit 15).

5.2.3

CLOCKRUN# Signal (82801BAM ICH2-M only)

5.2.3.1

PCI Power Management

Enhanced support for the power management standard, PCI specification rev. 2.2, is provided in

the ICH2 integrated LAN Controller. The LAN Controller supports a large set of wake-up packets

and the capability to wake the system from a low power state on a link status change. The LAN

Controller enables the host system to be in a sleep state and remain virtually connected to the

network.

After a power management event or link status change is detected, the LAN Controller will wake

the host system. The sections below describe these events, the LAN Controller power states, and

estimated power consumption at each power state.

The ICH2-M receives a free-running 33 MHz clock. It does not stop based on the CLKRUN#

signal and protocol. When the LAN controller runs cycles on the PCI bus, the ICH2-M makes sure

that the STP_PCI# signal is high indictating that the PCI clock is running. This is to make sure that

any PCI tracker will not get confused by transactions on the PCI bus with its PCI clock stopped.

82801BA Datasheet(PDF) 75 Page - Intel Corporation