82801BA datasheet(23/498 Pages) INTEL

23 / 498 page

82801BA ICH2 and 82801BAM ICH2-M

Datasheet

xxiii

Tables

1-1

Industry Specifications ..................................................................................1-1

1-2

PCI Devices and Functions...........................................................................1-3

2-1

Hub Interface Signals....................................................................................2-1

2-2

LAN Connect Interface Signals.....................................................................2-1

2-3

EEPROM Interface Signals...........................................................................2-2

2-4

Firmware Hub Interface Signals....................................................................2-2

2-5

PCI Interface Signals ....................................................................................2-2

2-6

IDE Interface Signals ....................................................................................2-5

2-7

LPC Interface Signals ...................................................................................2-6

2-8

Interrupt Signals............................................................................................2-6

2-9

USB Interface Signals...................................................................................2-7

2-10

Power Management Interface Signals ..........................................................2-7

2-11

Processor Interface Signals ..........................................................................2-9

2-12

SM Bus Interface Signals............................................................................2-10

2-13

System Management Interface Signals ......................................................2-10

2-14

Real Time Clock Interface...........................................................................2-11

2-15

Other Clocks ...............................................................................................2-11

2-16

Miscellaneous Signals ................................................................................2-11

2-17

AC’97 Link Signals......................................................................................2-12

2-18

General Purpose I/O Signals ......................................................................2-12

2-19

Power and Ground Signals .........................................................................2-13

2-20

Functional Strap Definitions ........................................................................2-14

2-21

Test Mode Selection ...................................................................................2-15

3-1

ICH2 Power Planes.......................................................................................3-1

3-2

Integrated Pull-Up and Pull-Down Resistors.................................................3-1

3-3

IDE Series Termination Resistors.................................................................3-2

3-4

Power Plane and States for Output and I/O Signals.....................................3-3

3-5

Power Plane for Input Signals.......................................................................3-6

5-1

Type 0 Configuration Cycle Device Number Translation ..............................5-5

5-2

I/O Control Hub 2 EEPROM Address Map .................................................5-18

5-3

LPC Cycle Types Supported.......................................................................5-21

5-4

Start Field Bit Definitions.............................................................................5-22

5-5

Cycle Type Bit Definitions ...........................................................................5-22

5-6

Transfer Size Bit Definition .........................................................................5-22

5-7

SYNC Bit Definition.....................................................................................5-23

5-8

ICH2 Response to Sync Failures................................................................5-23

5-9

DMA Transfer Size......................................................................................5-28

5-10

Address Shifting in 16-bit I/O DMA Transfers .............................................5-28

5-11

DMA Cycle vs. I/O Address ........................................................................5-32

5-12

PCI Data Bus vs. DMA I/O Port Size ..........................................................5-32

5-13

DMA I/O Cycle Width vs. BE[3:0]#..............................................................5-33

5-14

Counter Operating Modes...........................................................................5-39

5-15

Interrupt Controller Core Connections ........................................................5-41

5-16

Interrupt Status Registers ...........................................................................5-42

5-17

Content of Interrupt Vector Byte .................................................................5-42

5-18

APIC Interrupt Mapping ..............................................................................5-49

5-19

Arbitration Cycles........................................................................................5-50

5-20

APIC Message Formats..............................................................................5-51

5-21

EOI Message ..............................................................................................5-51

82801BA Datasheet(PDF) 23 Page - Intel Corporation

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